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Rename SlotIndexes to match how they are used.

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The old naming scheme (load/use/def/store) can be traced back to an old
linear scan article, but the names don't match how slots are actually
used.

The load and store slots are not needed after the deferred spill code
insertion framework was deleted.

The use and def slots don't make any sense because we are using
half-open intervals as is customary in C code, but the names suggest
closed intervals.  In reality, these slots were used to distinguish
early-clobber defs from normal defs.

The new naming scheme also has 4 slots, but the names match how the
slots are really used.  This is a purely mechanical renaming, but some
of the code makes a lot more sense now.

llvm-svn: 144503
This commit is contained in:
Jakob Stoklund Olesen 2011-11-13 20:45:27 +00:00
parent 0c7b1d7cf1
commit 9b34607bdf
15 changed files with 161 additions and 155 deletions
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2
include/llvm/CodeGen/LiveInterval.h
View File

@ -381,7 +381,7 @@ namespace llvm {
/// point is not contained in the half-open live range. It is usually the /// point is not contained in the half-open live range. It is usually the
/// getDefIndex() slot following its last use. /// getDefIndex() slot following its last use.
bool killedAt(SlotIndex index) const { bool killedAt(SlotIndex index) const {
const_iterator r = find(index.getUseIndex()); const_iterator r = find(index.getRegSlot(true));
return r != end() && r->end == index; return r != end() && r->end == index;
} }

104
include/llvm/CodeGen/SlotIndexes.h
View File

@ -83,7 +83,29 @@ namespace llvm {
friend class SlotIndexes; friend class SlotIndexes;
friend struct DenseMapInfo<SlotIndex>; friend struct DenseMapInfo<SlotIndex>;
enum Slot { LOAD, USE, DEF, STORE, NUM }; enum Slot {
/// Basic block boundary. Used for live ranges entering and leaving a
/// block without being live in the layout neighbor. Also used as the
/// def slot of PHI-defs.
Slot_Block,
/// Early-clobber register use/def slot. A live range defined at
/// Slot_EarlyCLobber interferes with normal live ranges killed at
/// Slot_Register. Also used as the kill slot for live ranges tied to an
/// early-clobber def.
Slot_EarlyClobber,
/// Normal register use/def slot. Normal instructions kill and define
/// register live ranges at this slot.
Slot_Register,
/// Dead def kill point. Kill slot for a live range that is defined by
/// the same instruction (Slot_Register or Slot_EarlyClobber), but isn't
/// used anywhere.
Slot_Dead,
Slot_Count
};
PointerIntPair<IndexListEntry*, 2, unsigned> lie; PointerIntPair<IndexListEntry*, 2, unsigned> lie;
@ -113,7 +135,7 @@ namespace llvm {
enum { enum {
/// The default distance between instructions as returned by distance(). /// The default distance between instructions as returned by distance().
/// This may vary as instructions are inserted and removed. /// This may vary as instructions are inserted and removed.
InstrDist = 4*NUM InstrDist = 4 * Slot_Count
}; };
static inline SlotIndex getEmptyKey() { static inline SlotIndex getEmptyKey() {
@ -191,64 +213,44 @@ namespace llvm {
return other.getIndex() - getIndex(); return other.getIndex() - getIndex();
} }
/// isLoad - Return true if this is a LOAD slot. /// isBlock - Returns true if this is a block boundary slot.
bool isLoad() const { bool isBlock() const { return getSlot() == Slot_Block; }
return getSlot() == LOAD;
}
/// isDef - Return true if this is a DEF slot. /// isEarlyClobber - Returns true if this is an early-clobber slot.
bool isDef() const { bool isEarlyClobber() const { return getSlot() == Slot_EarlyClobber; }
return getSlot() == DEF;
}
/// isUse - Return true if this is a USE slot. /// isRegister - Returns true if this is a normal register use/def slot.
bool isUse() const { /// Note that early-clobber slots may also be used for uses and defs.
return getSlot() == USE; bool isRegister() const { return getSlot() == Slot_Register; }
}
/// isStore - Return true if this is a STORE slot. /// isDead - Returns true if this is a dead def kill slot.
bool isStore() const { bool isDead() const { return getSlot() == Slot_Dead; }
return getSlot() == STORE;
}
/// Returns the base index for associated with this index. The base index /// Returns the base index for associated with this index. The base index
/// is the one associated with the LOAD slot for the instruction pointed to /// is the one associated with the Slot_Block slot for the instruction
/// by this index. /// pointed to by this index.
SlotIndex getBaseIndex() const { SlotIndex getBaseIndex() const {
return getLoadIndex(); return SlotIndex(&entry(), Slot_Block);
} }
/// Returns the boundary index for associated with this index. The boundary /// Returns the boundary index for associated with this index. The boundary
/// index is the one associated with the LOAD slot for the instruction /// index is the one associated with the Slot_Block slot for the instruction
/// pointed to by this index. /// pointed to by this index.
SlotIndex getBoundaryIndex() const { SlotIndex getBoundaryIndex() const {
return getStoreIndex(); return SlotIndex(&entry(), Slot_Dead);
} }
/// Returns the index of the LOAD slot for the instruction pointed to by /// Returns the register use/def slot in the current instruction for a
/// this index. /// normal or early-clobber def.
SlotIndex getLoadIndex() const { SlotIndex getRegSlot(bool EC = false) const {
return SlotIndex(&entry(), SlotIndex::LOAD); return SlotIndex(&entry(), EC ? Slot_EarlyClobber : Slot_Register);
}
/// Returns the index of the USE slot for the instruction pointed to by
/// this index.
SlotIndex getUseIndex() const {
return SlotIndex(&entry(), SlotIndex::USE);
} }
/// Returns the index of the DEF slot for the instruction pointed to by /// Returns the dead def kill slot for the current instruction.
/// this index. SlotIndex getDeadSlot() const {
SlotIndex getDefIndex() const { return SlotIndex(&entry(), Slot_Dead);
return SlotIndex(&entry(), SlotIndex::DEF);
} }
/// Returns the index of the STORE slot for the instruction pointed to by
/// this index.
SlotIndex getStoreIndex() const {
return SlotIndex(&entry(), SlotIndex::STORE);
}
/// Returns the next slot in the index list. This could be either the /// Returns the next slot in the index list. This could be either the
/// next slot for the instruction pointed to by this index or, if this /// next slot for the instruction pointed to by this index or, if this
/// index is a STORE, the first slot for the next instruction. /// index is a STORE, the first slot for the next instruction.
@ -257,8 +259,8 @@ namespace llvm {
/// use one of those methods. /// use one of those methods.
SlotIndex getNextSlot() const { SlotIndex getNextSlot() const {
Slot s = getSlot(); Slot s = getSlot();
if (s == SlotIndex::STORE) { if (s == Slot_Dead) {
return SlotIndex(entry().getNext(), SlotIndex::LOAD); return SlotIndex(entry().getNext(), Slot_Block);
} }
return SlotIndex(&entry(), s + 1); return SlotIndex(&entry(), s + 1);
} }
@ -271,14 +273,14 @@ namespace llvm {
/// Returns the previous slot in the index list. This could be either the /// Returns the previous slot in the index list. This could be either the
/// previous slot for the instruction pointed to by this index or, if this /// previous slot for the instruction pointed to by this index or, if this
/// index is a LOAD, the last slot for the previous instruction. /// index is a Slot_Block, the last slot for the previous instruction.
/// WARNING: This method is considerably more expensive than the methods /// WARNING: This method is considerably more expensive than the methods
/// that return specific slots (getUseIndex(), etc). If you can - please /// that return specific slots (getUseIndex(), etc). If you can - please
/// use one of those methods. /// use one of those methods.
SlotIndex getPrevSlot() const { SlotIndex getPrevSlot() const {
Slot s = getSlot(); Slot s = getSlot();
if (s == SlotIndex::LOAD) { if (s == Slot_Block) {
return SlotIndex(entry().getPrev(), SlotIndex::STORE); return SlotIndex(entry().getPrev(), Slot_Dead);
} }
return SlotIndex(&entry(), s - 1); return SlotIndex(&entry(), s - 1);
} }
@ -677,7 +679,7 @@ namespace llvm {
if (dist == 0) if (dist == 0)
renumberIndexes(newEntry); renumberIndexes(newEntry);
SlotIndex newIndex(newEntry, SlotIndex::LOAD); SlotIndex newIndex(newEntry, SlotIndex::Slot_Block);
mi2iMap.insert(std::make_pair(mi, newIndex)); mi2iMap.insert(std::make_pair(mi, newIndex));
return newIndex; return newIndex;
} }
@ -728,8 +730,8 @@ namespace llvm {
insert(nextEntry, startEntry); insert(nextEntry, startEntry);
insert(nextEntry, stopEntry); insert(nextEntry, stopEntry);
SlotIndex startIdx(startEntry, SlotIndex::LOAD); SlotIndex startIdx(startEntry, SlotIndex::Slot_Block);
SlotIndex endIdx(nextEntry, SlotIndex::LOAD); SlotIndex endIdx(nextEntry, SlotIndex::Slot_Block);
assert(unsigned(mbb->getNumber()) == MBBRanges.size() && assert(unsigned(mbb->getNumber()) == MBBRanges.size() &&
"Blocks must be added in order"); "Blocks must be added in order");

24
lib/CodeGen/InlineSpiller.cpp
View File

@ -578,7 +578,7 @@ MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
if (unsigned SrcReg = isFullCopyOf(MI, Reg)) { if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
if (isSibling(SrcReg)) { if (isSibling(SrcReg)) {
LiveInterval &SrcLI = LIS.getInterval(SrcReg); LiveInterval &SrcLI = LIS.getInterval(SrcReg);
LiveRange *SrcLR = SrcLI.getLiveRangeContaining(VNI->def.getUseIndex()); LiveRange *SrcLR = SrcLI.getLiveRangeContaining(VNI->def.getRegSlot(true));
assert(SrcLR && "Copy from non-existing value"); assert(SrcLR && "Copy from non-existing value");
// Check if this COPY kills its source. // Check if this COPY kills its source.
SVI->second.KillsSource = (SrcLR->end == VNI->def); SVI->second.KillsSource = (SrcLR->end == VNI->def);
@ -665,8 +665,8 @@ void InlineSpiller::analyzeSiblingValues() {
/// a spill at a better location. /// a spill at a better location.
bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) { bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
SlotIndex Idx = LIS.getInstructionIndex(CopyMI); SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getDefIndex()); VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
assert(VNI && VNI->def == Idx.getDefIndex() && "Not defined by copy"); assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
SibValueMap::iterator I = SibValues.find(VNI); SibValueMap::iterator I = SibValues.find(VNI);
if (I == SibValues.end()) if (I == SibValues.end())
return false; return false;
@ -769,9 +769,9 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
if (unsigned DstReg = isFullCopyOf(MI, Reg)) { if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
if (isSibling(DstReg)) { if (isSibling(DstReg)) {
LiveInterval &DstLI = LIS.getInterval(DstReg); LiveInterval &DstLI = LIS.getInterval(DstReg);
VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getDefIndex()); VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
assert(DstVNI && "Missing defined value"); assert(DstVNI && "Missing defined value");
assert(DstVNI->def == Idx.getDefIndex() && "Wrong copy def slot"); assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
WorkList.push_back(std::make_pair(&DstLI, DstVNI)); WorkList.push_back(std::make_pair(&DstLI, DstVNI));
} }
continue; continue;
@ -823,7 +823,7 @@ void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
continue; continue;
LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg()); LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy"); assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getUseIndex()); VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
assert(SnipVNI && "Snippet undefined before copy"); assert(SnipVNI && "Snippet undefined before copy");
WorkList.push_back(std::make_pair(&SnipLI, SnipVNI)); WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
} while (!WorkList.empty()); } while (!WorkList.empty());
@ -832,7 +832,7 @@ void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading. /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
MachineBasicBlock::iterator MI) { MachineBasicBlock::iterator MI) {
SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex(); SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
if (!ParentVNI) { if (!ParentVNI) {
@ -906,7 +906,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI); DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, LIS.getVNInfoAllocator()); VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, LIS.getVNInfoAllocator());
NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI)); NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI));
DEBUG(dbgs() << "\tinterval: " << NewLI << '\n'); DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
++NumRemats; ++NumRemats;
return true; return true;
@ -1077,7 +1077,7 @@ void InlineSpiller::insertReload(LiveInterval &NewLI,
TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot, TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
MRI.getRegClass(NewLI.reg), &TRI); MRI.getRegClass(NewLI.reg), &TRI);
--MI; // Point to load instruction. --MI; // Point to load instruction.
SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex(); SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getRegSlot();
DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI); DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0,
LIS.getVNInfoAllocator()); LIS.getVNInfoAllocator());
@ -1092,7 +1092,7 @@ void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot, TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
MRI.getRegClass(NewLI.reg), &TRI); MRI.getRegClass(NewLI.reg), &TRI);
--MI; // Point to store instruction. --MI; // Point to store instruction.
SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex(); SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getRegSlot();
DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI); DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, LIS.getVNInfoAllocator()); VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, LIS.getVNInfoAllocator());
NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI)); NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
@ -1141,8 +1141,8 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
// Find the slot index where this instruction reads and writes OldLI. // Find the slot index where this instruction reads and writes OldLI.
// This is usually the def slot, except for tied early clobbers. // This is usually the def slot, except for tied early clobbers.
SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex(); SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getUseIndex())) if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
if (SlotIndex::isSameInstr(Idx, VNI->def)) if (SlotIndex::isSameInstr(Idx, VNI->def))
Idx = VNI->def; Idx = VNI->def;

8
lib/CodeGen/LiveDebugVariables.cpp
View File

@ -468,7 +468,7 @@ bool LDVImpl::collectDebugValues(MachineFunction &mf) {
// DBG_VALUE has no slot index, use the previous instruction instead. // DBG_VALUE has no slot index, use the previous instruction instead.
SlotIndex Idx = MBBI == MBB->begin() ? SlotIndex Idx = MBBI == MBB->begin() ?
LIS->getMBBStartIdx(MBB) : LIS->getMBBStartIdx(MBB) :
LIS->getInstructionIndex(llvm::prior(MBBI)).getDefIndex(); LIS->getInstructionIndex(llvm::prior(MBBI)).getRegSlot();
// Handle consecutive DBG_VALUE instructions with the same slot index. // Handle consecutive DBG_VALUE instructions with the same slot index.
do { do {
if (handleDebugValue(MBBI, Idx)) { if (handleDebugValue(MBBI, Idx)) {
@ -575,15 +575,15 @@ UserValue::addDefsFromCopies(LiveInterval *LI, unsigned LocNo,
// Is LocNo extended to reach this copy? If not, another def may be blocking // Is LocNo extended to reach this copy? If not, another def may be blocking
// it, or we are looking at a wrong value of LI. // it, or we are looking at a wrong value of LI.
SlotIndex Idx = LIS.getInstructionIndex(MI); SlotIndex Idx = LIS.getInstructionIndex(MI);
LocMap::iterator I = locInts.find(Idx.getUseIndex()); LocMap::iterator I = locInts.find(Idx.getRegSlot(true));
if (!I.valid() || I.value() != LocNo) if (!I.valid() || I.value() != LocNo)
continue; continue;
if (!LIS.hasInterval(DstReg)) if (!LIS.hasInterval(DstReg))
continue; continue;
LiveInterval *DstLI = &LIS.getInterval(DstReg); LiveInterval *DstLI = &LIS.getInterval(DstReg);
const VNInfo *DstVNI = DstLI->getVNInfoAt(Idx.getDefIndex()); const VNInfo *DstVNI = DstLI->getVNInfoAt(Idx.getRegSlot());
assert(DstVNI && DstVNI->def == Idx.getDefIndex() && "Bad copy value"); assert(DstVNI && DstVNI->def == Idx.getRegSlot() && "Bad copy value");
CopyValues.push_back(std::make_pair(DstLI, DstVNI)); CopyValues.push_back(std::make_pair(DstLI, DstVNI));
} }

2
lib/CodeGen/LiveInterval.cpp
View File

@ -716,7 +716,7 @@ void ConnectedVNInfoEqClasses::Distribute(LiveInterval *LIV[],
continue; continue;
// DBG_VALUE instructions should have been eliminated earlier. // DBG_VALUE instructions should have been eliminated earlier.
SlotIndex Idx = LIS.getInstructionIndex(MI); SlotIndex Idx = LIS.getInstructionIndex(MI);
Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex(); Idx = Idx.getRegSlot(MO.isUse());
const VNInfo *VNI = LI.getVNInfoAt(Idx); const VNInfo *VNI = LI.getVNInfoAt(Idx);
assert(VNI && "Interval not live at use."); assert(VNI && "Interval not live at use.");
MO.setReg(LIV[getEqClass(VNI)]->reg); MO.setReg(LIV[getEqClass(VNI)]->reg);

64
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -172,9 +172,9 @@ bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
if (!MO.getSubReg() || MO.isEarlyClobber()) if (!MO.getSubReg() || MO.isEarlyClobber())
return false; return false;
SlotIndex RedefIndex = MIIdx.getDefIndex(); SlotIndex RedefIndex = MIIdx.getRegSlot();
const LiveRange *OldLR = const LiveRange *OldLR =
interval.getLiveRangeContaining(RedefIndex.getUseIndex()); interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def); MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
if (DefMI != 0) { if (DefMI != 0) {
return DefMI->findRegisterDefOperandIdx(interval.reg) != -1; return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
@ -197,11 +197,11 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
if (interval.empty()) { if (interval.empty()) {
// Get the Idx of the defining instructions. // Get the Idx of the defining instructions.
SlotIndex defIndex = MIIdx.getDefIndex(); SlotIndex defIndex = MIIdx.getRegSlot();
// Earlyclobbers move back one, so that they overlap the live range // Earlyclobbers move back one, so that they overlap the live range
// of inputs. // of inputs.
if (MO.isEarlyClobber()) if (MO.isEarlyClobber())
defIndex = MIIdx.getUseIndex(); defIndex = MIIdx.getRegSlot(true);
// Make sure the first definition is not a partial redefinition. Add an // Make sure the first definition is not a partial redefinition. Add an
// <imp-def> of the full register. // <imp-def> of the full register.
@ -235,9 +235,9 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// FIXME: what about dead vars? // FIXME: what about dead vars?
SlotIndex killIdx; SlotIndex killIdx;
if (vi.Kills[0] != mi) if (vi.Kills[0] != mi)
killIdx = getInstructionIndex(vi.Kills[0]).getDefIndex(); killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
else else
killIdx = defIndex.getStoreIndex(); killIdx = defIndex.getDeadSlot();
// If the kill happens after the definition, we have an intra-block // If the kill happens after the definition, we have an intra-block
// live range. // live range.
@ -285,7 +285,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
MachineInstr *Kill = vi.Kills[i]; MachineInstr *Kill = vi.Kills[i];
SlotIndex Start = getMBBStartIdx(Kill->getParent()); SlotIndex Start = getMBBStartIdx(Kill->getParent());
SlotIndex killIdx = getInstructionIndex(Kill).getDefIndex(); SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
// Create interval with one of a NEW value number. Note that this value // Create interval with one of a NEW value number. Note that this value
// number isn't actually defined by an instruction, weird huh? :) // number isn't actually defined by an instruction, weird huh? :)
@ -323,14 +323,14 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// are actually two values in the live interval. Because of this we // are actually two values in the live interval. Because of this we
// need to take the LiveRegion that defines this register and split it // need to take the LiveRegion that defines this register and split it
// into two values. // into two values.
SlotIndex RedefIndex = MIIdx.getDefIndex(); SlotIndex RedefIndex = MIIdx.getRegSlot();
if (MO.isEarlyClobber()) if (MO.isEarlyClobber())
RedefIndex = MIIdx.getUseIndex(); RedefIndex = MIIdx.getRegSlot(true);
const LiveRange *OldLR = const LiveRange *OldLR =
interval.getLiveRangeContaining(RedefIndex.getUseIndex()); interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
VNInfo *OldValNo = OldLR->valno; VNInfo *OldValNo = OldLR->valno;
SlotIndex DefIndex = OldValNo->def.getDefIndex(); SlotIndex DefIndex = OldValNo->def.getRegSlot();
// Delete the previous value, which should be short and continuous, // Delete the previous value, which should be short and continuous,
// because the 2-addr copy must be in the same MBB as the redef. // because the 2-addr copy must be in the same MBB as the redef.
@ -356,7 +356,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// If this redefinition is dead, we need to add a dummy unit live // If this redefinition is dead, we need to add a dummy unit live
// range covering the def slot. // range covering the def slot.
if (MO.isDead()) if (MO.isDead())
interval.addRange(LiveRange(RedefIndex, RedefIndex.getStoreIndex(), interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
OldValNo)); OldValNo));
DEBUG({ DEBUG({
@ -368,9 +368,9 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// live until the end of the block. We've already taken care of the // live until the end of the block. We've already taken care of the
// rest of the live range. // rest of the live range.
SlotIndex defIndex = MIIdx.getDefIndex(); SlotIndex defIndex = MIIdx.getRegSlot();
if (MO.isEarlyClobber()) if (MO.isEarlyClobber())
defIndex = MIIdx.getUseIndex(); defIndex = MIIdx.getRegSlot(true);
VNInfo *ValNo; VNInfo *ValNo;
MachineInstr *CopyMI = NULL; MachineInstr *CopyMI = NULL;
@ -402,10 +402,10 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_)); DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
SlotIndex baseIndex = MIIdx; SlotIndex baseIndex = MIIdx;
SlotIndex start = baseIndex.getDefIndex(); SlotIndex start = baseIndex.getRegSlot();
// Earlyclobbers move back one. // Earlyclobbers move back one.
if (MO.isEarlyClobber()) if (MO.isEarlyClobber())
start = MIIdx.getUseIndex(); start = MIIdx.getRegSlot(true);
SlotIndex end = start; SlotIndex end = start;
// If it is not used after definition, it is considered dead at // If it is not used after definition, it is considered dead at
@ -415,7 +415,7 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
// advance below compensates. // advance below compensates.
if (MO.isDead()) { if (MO.isDead()) {
DEBUG(dbgs() << " dead"); DEBUG(dbgs() << " dead");
end = start.getStoreIndex(); end = start.getDeadSlot();
goto exit; goto exit;
} }
@ -432,21 +432,21 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
if (mi->killsRegister(interval.reg, tri_)) { if (mi->killsRegister(interval.reg, tri_)) {
DEBUG(dbgs() << " killed"); DEBUG(dbgs() << " killed");
end = baseIndex.getDefIndex(); end = baseIndex.getRegSlot();
goto exit; goto exit;
} else { } else {
int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_); int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
if (DefIdx != -1) { if (DefIdx != -1) {
if (mi->isRegTiedToUseOperand(DefIdx)) { if (mi->isRegTiedToUseOperand(DefIdx)) {
// Two-address instruction. // Two-address instruction.
end = baseIndex.getDefIndex(); end = baseIndex.getRegSlot();
} else { } else {
// Another instruction redefines the register before it is ever read. // Another instruction redefines the register before it is ever read.
// Then the register is essentially dead at the instruction that // Then the register is essentially dead at the instruction that
// defines it. Hence its interval is: // defines it. Hence its interval is:
// [defSlot(def), defSlot(def)+1) // [defSlot(def), defSlot(def)+1)
DEBUG(dbgs() << " dead"); DEBUG(dbgs() << " dead");
end = start.getStoreIndex(); end = start.getDeadSlot();
} }
goto exit; goto exit;
} }
@ -459,7 +459,7 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
// instruction where we know it's dead is if it is live-in to the function // instruction where we know it's dead is if it is live-in to the function
// and never used. Another possible case is the implicit use of the // and never used. Another possible case is the implicit use of the
// physical register has been deleted by two-address pass. // physical register has been deleted by two-address pass.
end = start.getStoreIndex(); end = start.getDeadSlot();
exit: exit:
assert(start < end && "did not find end of interval?"); assert(start < end && "did not find end of interval?");
@ -522,7 +522,7 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
while (mi != E) { while (mi != E) {
if (mi->killsRegister(interval.reg, tri_)) { if (mi->killsRegister(interval.reg, tri_)) {
DEBUG(dbgs() << " killed"); DEBUG(dbgs() << " killed");
end = baseIndex.getDefIndex(); end = baseIndex.getRegSlot();
SeenDefUse = true; SeenDefUse = true;
break; break;
} else if (mi->definesRegister(interval.reg, tri_)) { } else if (mi->definesRegister(interval.reg, tri_)) {
@ -531,7 +531,7 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
// it. Hence its interval is: // it. Hence its interval is:
// [defSlot(def), defSlot(def)+1) // [defSlot(def), defSlot(def)+1)
DEBUG(dbgs() << " dead"); DEBUG(dbgs() << " dead");
end = start.getStoreIndex(); end = start.getDeadSlot();
SeenDefUse = true; SeenDefUse = true;
break; break;
} }
@ -547,7 +547,7 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
if (!SeenDefUse) { if (!SeenDefUse) {
if (isAlias) { if (isAlias) {
DEBUG(dbgs() << " dead"); DEBUG(dbgs() << " dead");
end = MIIdx.getStoreIndex(); end = MIIdx.getDeadSlot();
} else { } else {
DEBUG(dbgs() << " live through"); DEBUG(dbgs() << " live through");
end = getMBBEndIdx(MBB); end = getMBBEndIdx(MBB);
@ -667,7 +667,7 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
MachineInstr *UseMI = I.skipInstruction();) { MachineInstr *UseMI = I.skipInstruction();) {
if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg)) if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
continue; continue;
SlotIndex Idx = getInstructionIndex(UseMI).getUseIndex(); SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot(true);
VNInfo *VNI = li->getVNInfoAt(Idx); VNInfo *VNI = li->getVNInfoAt(Idx);
if (!VNI) { if (!VNI) {
// This shouldn't happen: readsVirtualRegister returns true, but there is // This shouldn't happen: readsVirtualRegister returns true, but there is
@ -700,9 +700,9 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
// A use tied to an early-clobber def ends at the load slot and isn't caught // A use tied to an early-clobber def ends at the load slot and isn't caught
// above. Catch it here instead. This probably only ever happens for inline // above. Catch it here instead. This probably only ever happens for inline
// assembly. // assembly.
if (VNI->def.isUse()) if (VNI->def.isEarlyClobber())
if (VNInfo *UVNI = li->getVNInfoAt(VNI->def.getLoadIndex())) if (VNInfo *UVNI = li->getVNInfoBefore(VNI->def))
WorkList.push_back(std::make_pair(VNI->def.getLoadIndex(), UVNI)); WorkList.push_back(std::make_pair(VNI->def.getPrevSlot(), UVNI));
} }
// Keep track of the PHIs that are in use. // Keep track of the PHIs that are in use.
@ -825,8 +825,8 @@ void LiveIntervals::addKillFlags() {
// Every instruction that kills Reg corresponds to a live range end point. // Every instruction that kills Reg corresponds to a live range end point.
for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE; for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
++RI) { ++RI) {
// A LOAD index indicates an MBB edge. // A block index indicates an MBB edge.
if (RI->end.isLoad()) if (RI->end.isBlock())
continue; continue;
MachineInstr *MI = getInstructionFromIndex(RI->end); MachineInstr *MI = getInstructionFromIndex(RI->end);
if (!MI) if (!MI)
@ -978,11 +978,11 @@ LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
MachineInstr* startInst) { MachineInstr* startInst) {
LiveInterval& Interval = getOrCreateInterval(reg); LiveInterval& Interval = getOrCreateInterval(reg);
VNInfo* VN = Interval.getNextValue( VNInfo* VN = Interval.getNextValue(
SlotIndex(getInstructionIndex(startInst).getDefIndex()), SlotIndex(getInstructionIndex(startInst).getRegSlot()),
startInst, getVNInfoAllocator()); startInst, getVNInfoAllocator());
VN->setHasPHIKill(true); VN->setHasPHIKill(true);
LiveRange LR( LiveRange LR(
SlotIndex(getInstructionIndex(startInst).getDefIndex()), SlotIndex(getInstructionIndex(startInst).getRegSlot()),
getMBBEndIdx(startInst->getParent()), VN); getMBBEndIdx(startInst->getParent()), VN);
Interval.addRange(LR); Interval.addRange(LR);

8
lib/CodeGen/LiveRangeEdit.cpp
View File

@ -83,8 +83,8 @@ bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
SlotIndex OrigIdx, SlotIndex OrigIdx,
SlotIndex UseIdx, SlotIndex UseIdx,
LiveIntervals &lis) { LiveIntervals &lis) {
OrigIdx = OrigIdx.getUseIndex(); OrigIdx = OrigIdx.getRegSlot(true);
UseIdx = UseIdx.getUseIndex(); UseIdx = UseIdx.getRegSlot(true);
for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = OrigMI->getOperand(i); const MachineOperand &MO = OrigMI->getOperand(i);
if (!MO.isReg() || !MO.getReg() || MO.isDef()) if (!MO.isReg() || !MO.getReg() || MO.isDef())
@ -151,7 +151,7 @@ SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri); tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
rematted_.insert(RM.ParentVNI); rematted_.insert(RM.ParentVNI);
return lis.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late) return lis.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
.getDefIndex(); .getRegSlot();
} }
void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) { void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
@ -221,7 +221,7 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
while (!Dead.empty()) { while (!Dead.empty()) {
MachineInstr *MI = Dead.pop_back_val(); MachineInstr *MI = Dead.pop_back_val();
assert(MI->allDefsAreDead() && "Def isn't really dead"); assert(MI->allDefsAreDead() && "Def isn't really dead");
SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex(); SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
// Never delete inline asm. // Never delete inline asm.
if (MI->isInlineAsm()) { if (MI->isInlineAsm()) {

19
lib/CodeGen/MachineVerifier.cpp
View File

@ -659,7 +659,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// Check LiveInts liveness and kill. // Check LiveInts liveness and kill.
if (TargetRegisterInfo::isVirtualRegister(Reg) && if (TargetRegisterInfo::isVirtualRegister(Reg) &&
LiveInts && !LiveInts->isNotInMIMap(MI)) { LiveInts && !LiveInts->isNotInMIMap(MI)) {
SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex(); SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getRegSlot(true);
if (LiveInts->hasInterval(Reg)) { if (LiveInts->hasInterval(Reg)) {
const LiveInterval &LI = LiveInts->getInterval(Reg); const LiveInterval &LI = LiveInts->getInterval(Reg);
if (!LI.liveAt(UseIdx)) { if (!LI.liveAt(UseIdx)) {
@ -668,7 +668,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
} }
// Check for extra kill flags. // Check for extra kill flags.
// Note that we allow missing kill flags for now. // Note that we allow missing kill flags for now.
if (MO->isKill() && !LI.killedAt(UseIdx.getDefIndex())) { if (MO->isKill() && !LI.killedAt(UseIdx.getRegSlot())) {
report("Live range continues after kill flag", MO, MONum); report("Live range continues after kill flag", MO, MONum);
*OS << "Live range: " << LI << '\n'; *OS << "Live range: " << LI << '\n';
} }
@ -710,7 +710,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// Check LiveInts for a live range, but only for virtual registers. // Check LiveInts for a live range, but only for virtual registers.
if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) && if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
!LiveInts->isNotInMIMap(MI)) { !LiveInts->isNotInMIMap(MI)) {
SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex(); SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getRegSlot();
if (LiveInts->hasInterval(Reg)) { if (LiveInts->hasInterval(Reg)) {
const LiveInterval &LI = LiveInts->getInterval(Reg); const LiveInterval &LI = LiveInts->getInterval(Reg);
if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
@ -800,11 +800,11 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
LiveInts && !LiveInts->isNotInMIMap(MI)) { LiveInts && !LiveInts->isNotInMIMap(MI)) {
LiveInterval &LI = LiveStks->getInterval(MO->getIndex()); LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
SlotIndex Idx = LiveInts->getInstructionIndex(MI); SlotIndex Idx = LiveInts->getInstructionIndex(MI);
if (MCID.mayLoad() && !LI.liveAt(Idx.getUseIndex())) { if (MCID.mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
report("Instruction loads from dead spill slot", MO, MONum); report("Instruction loads from dead spill slot", MO, MONum);
*OS << "Live stack: " << LI << '\n'; *OS << "Live stack: " << LI << '\n';
} }
if (MCID.mayStore() && !LI.liveAt(Idx.getDefIndex())) { if (MCID.mayStore() && !LI.liveAt(Idx.getRegSlot())) {
report("Instruction stores to dead spill slot", MO, MONum); report("Instruction stores to dead spill slot", MO, MONum);
*OS << "Live stack: " << LI << '\n'; *OS << "Live stack: " << LI << '\n';
} }
@ -1085,13 +1085,14 @@ void MachineVerifier::verifyLiveIntervals() {
// Early clobber defs begin at USE slots, but other defs must begin at // Early clobber defs begin at USE slots, but other defs must begin at
// DEF slots. // DEF slots.
if (isEarlyClobber) { if (isEarlyClobber) {
if (!VNI->def.isUse()) { if (!VNI->def.isEarlyClobber()) {
report("Early clobber def must be at a USE slot", MF); report("Early clobber def must be at an early-clobber slot", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n'; << " in " << LI << '\n';
} }
} else if (!VNI->def.isDef()) { } else if (!VNI->def.isRegister()) {
report("Non-PHI, non-early clobber def must be at a DEF slot", MF); report("Non-PHI, non-early clobber def must be at a register slot",
MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n'; << " in " << LI << '\n';
} }

22
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -423,7 +423,7 @@ bool RegisterCoalescer::AdjustCopiesBackFrom(const CoalescerPair &CP,
LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
LiveInterval &IntB = LiveInterval &IntB =
LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getDefIndex(); SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
// BValNo is a value number in B that is defined by a copy from A. 'B3' in // BValNo is a value number in B that is defined by a copy from A. 'B3' in
// the example above. // the example above.
@ -438,7 +438,7 @@ bool RegisterCoalescer::AdjustCopiesBackFrom(const CoalescerPair &CP,
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
// AValNo is the value number in A that defines the copy, A3 in the example. // AValNo is the value number in A that defines the copy, A3 in the example.
SlotIndex CopyUseIdx = CopyIdx.getUseIndex(); SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx); LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
// The live range might not exist after fun with physreg coalescing. // The live range might not exist after fun with physreg coalescing.
if (ALR == IntA.end()) return false; if (ALR == IntA.end()) return false;
@ -625,7 +625,7 @@ bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP,
if (!LIS->hasInterval(CP.getDstReg())) if (!LIS->hasInterval(CP.getDstReg()))
return false; return false;
SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getDefIndex(); SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
LiveInterval &IntA = LiveInterval &IntA =
LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
@ -641,7 +641,7 @@ bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP,
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
// AValNo is the value number in A that defines the copy, A3 in the example. // AValNo is the value number in A that defines the copy, A3 in the example.
VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getUseIndex()); VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
assert(AValNo && "COPY source not live"); assert(AValNo && "COPY source not live");
// If other defs can reach uses of this def, then it's not safe to perform // If other defs can reach uses of this def, then it's not safe to perform
@ -747,7 +747,7 @@ bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP,
UseMO.setReg(NewReg); UseMO.setReg(NewReg);
continue; continue;
} }
SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getUseIndex(); SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
if (ULR == IntA.end() || ULR->valno != AValNo) if (ULR == IntA.end() || ULR->valno != AValNo)
continue; continue;
@ -765,7 +765,7 @@ bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP,
// This copy will become a noop. If it's defining a new val#, merge it into // This copy will become a noop. If it's defining a new val#, merge it into
// BValNo. // BValNo.
SlotIndex DefIdx = UseIdx.getDefIndex(); SlotIndex DefIdx = UseIdx.getRegSlot();
VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
if (!DVNI) if (!DVNI)
continue; continue;
@ -799,7 +799,7 @@ bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
bool preserveSrcInt, bool preserveSrcInt,
unsigned DstReg, unsigned DstReg,
MachineInstr *CopyMI) { MachineInstr *CopyMI) {
SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getUseIndex(); SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx); LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
assert(SrcLR != SrcInt.end() && "Live range not found!"); assert(SrcLR != SrcInt.end() && "Live range not found!");
VNInfo *ValNo = SrcLR->valno; VNInfo *ValNo = SrcLR->valno;
@ -887,7 +887,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
DstInt = SrcInt; DstInt = SrcInt;
SrcInt = 0; SrcInt = 0;
VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getDefIndex()); VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
assert(DeadVNI && "No value defined in DstInt"); assert(DeadVNI && "No value defined in DstInt");
DstInt->removeValNo(DeadVNI); DstInt->removeValNo(DeadVNI);
@ -1013,7 +1013,7 @@ static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
/// the val# it defines. If the live interval becomes empty, remove it as well. /// the val# it defines. If the live interval becomes empty, remove it as well.
bool RegisterCoalescer::RemoveDeadDef(LiveInterval &li, bool RegisterCoalescer::RemoveDeadDef(LiveInterval &li,
MachineInstr *DefMI) { MachineInstr *DefMI) {
SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getDefIndex(); SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot();
LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx); LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
if (DefIdx != MLR->valno->def) if (DefIdx != MLR->valno->def)
return false; return false;
@ -1023,7 +1023,7 @@ bool RegisterCoalescer::RemoveDeadDef(LiveInterval &li,
void RegisterCoalescer::RemoveCopyFlag(unsigned DstReg, void RegisterCoalescer::RemoveCopyFlag(unsigned DstReg,
const MachineInstr *CopyMI) { const MachineInstr *CopyMI) {
SlotIndex DefIdx = LIS->getInstructionIndex(CopyMI).getDefIndex(); SlotIndex DefIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
if (LIS->hasInterval(DstReg)) { if (LIS->hasInterval(DstReg)) {
LiveInterval &LI = LIS->getInterval(DstReg); LiveInterval &LI = LIS->getInterval(DstReg);
if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx)) if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
@ -1936,7 +1936,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
// Check for now unnecessary kill flags. // Check for now unnecessary kill flags.
if (LIS->isNotInMIMap(MI)) continue; if (LIS->isNotInMIMap(MI)) continue;
SlotIndex DefIdx = LIS->getInstructionIndex(MI).getDefIndex(); SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isKill()) continue; if (!MO.isReg() || !MO.isKill()) continue;

17
lib/CodeGen/RenderMachineFunction.cpp
View File

@ -560,12 +560,13 @@ namespace llvm {
// For uses/defs recorded use/def indexes override current liveness and // For uses/defs recorded use/def indexes override current liveness and
// instruction operands (Only for the interval which records the indexes). // instruction operands (Only for the interval which records the indexes).
if (i.isUse() || i.isDef()) { // FIXME: This is all wrong, uses and defs share the same slots.
if (i.isEarlyClobber() || i.isRegister()) {
UseDefs::const_iterator udItr = useDefs.find(li); UseDefs::const_iterator udItr = useDefs.find(li);
if (udItr != useDefs.end()) { if (udItr != useDefs.end()) {
const SlotSet &slotSet = udItr->second; const SlotSet &slotSet = udItr->second;
if (slotSet.count(i)) { if (slotSet.count(i)) {
if (i.isUse()) { if (i.isEarlyClobber()) {
return Used; return Used;
} }
// else // else
@ -586,9 +587,9 @@ namespace llvm {
return AliveStack; return AliveStack;
} }
} else { } else {
if (i.isDef() && mi->definesRegister(li->reg, tri)) { if (i.isRegister() && mi->definesRegister(li->reg, tri)) {
return Defined; return Defined;
} else if (i.isUse() && mi->readsRegister(li->reg)) { } else if (i.isEarlyClobber() && mi->readsRegister(li->reg)) {
return Used; return Used;
} else { } else {
if (vrm == 0 || if (vrm == 0 ||
@ -804,7 +805,7 @@ namespace llvm {
os << indent + s(2) << "<tr height=6ex>\n"; os << indent + s(2) << "<tr height=6ex>\n";
// Render the code column. // Render the code column.
if (i.isLoad()) { if (i.isBlock()) {
MachineBasicBlock *mbb = sis->getMBBFromIndex(i); MachineBasicBlock *mbb = sis->getMBBFromIndex(i);
mi = sis->getInstructionFromIndex(i); mi = sis->getInstructionFromIndex(i);
@ -823,7 +824,7 @@ namespace llvm {
} }
os << indent + s(4) << "</td>\n"; os << indent + s(4) << "</td>\n";
} else { } else {
i = i.getStoreIndex(); // <- Will be incremented to the next index. i = i.getDeadSlot(); // <- Will be incremented to the next index.
continue; continue;
} }
} }
@ -952,10 +953,10 @@ namespace llvm {
rItr != rEnd; ++rItr) { rItr != rEnd; ++rItr) {
const MachineInstr *mi = &*rItr; const MachineInstr *mi = &*rItr;
if (mi->readsRegister(li->reg)) { if (mi->readsRegister(li->reg)) {
useDefs[li].insert(lis->getInstructionIndex(mi).getUseIndex()); useDefs[li].insert(lis->getInstructionIndex(mi).getRegSlot(true));
} }
if (mi->definesRegister(li->reg)) { if (mi->definesRegister(li->reg)) {
useDefs[li].insert(lis->getInstructionIndex(mi).getDefIndex()); useDefs[li].insert(lis->getInstructionIndex(mi).getRegSlot());
} }
} }
} }

10
lib/CodeGen/SlotIndexes.cpp
View File

@ -76,7 +76,7 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) {
MachineBasicBlock *mbb = &*mbbItr; MachineBasicBlock *mbb = &*mbbItr;
// Insert an index for the MBB start. // Insert an index for the MBB start.
SlotIndex blockStartIndex(back(), SlotIndex::LOAD); SlotIndex blockStartIndex(back(), SlotIndex::Slot_Block);
for (MachineBasicBlock::iterator miItr = mbb->begin(), miEnd = mbb->end(); for (MachineBasicBlock::iterator miItr = mbb->begin(), miEnd = mbb->end();
miItr != miEnd; ++miItr) { miItr != miEnd; ++miItr) {
@ -88,7 +88,8 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) {
push_back(createEntry(mi, index += SlotIndex::InstrDist)); push_back(createEntry(mi, index += SlotIndex::InstrDist));
// Save this base index in the maps. // Save this base index in the maps.
mi2iMap.insert(std::make_pair(mi, SlotIndex(back(), SlotIndex::LOAD))); mi2iMap.insert(std::make_pair(mi, SlotIndex(back(),
SlotIndex::Slot_Block)));
++functionSize; ++functionSize;
} }
@ -97,7 +98,8 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) {
push_back(createEntry(0, index += SlotIndex::InstrDist)); push_back(createEntry(0, index += SlotIndex::InstrDist));
MBBRanges[mbb->getNumber()].first = blockStartIndex; MBBRanges[mbb->getNumber()].first = blockStartIndex;
MBBRanges[mbb->getNumber()].second = SlotIndex(back(), SlotIndex::LOAD); MBBRanges[mbb->getNumber()].second = SlotIndex(back(),
SlotIndex::Slot_Block);
idx2MBBMap.push_back(IdxMBBPair(blockStartIndex, mbb)); idx2MBBMap.push_back(IdxMBBPair(blockStartIndex, mbb));
} }
@ -166,7 +168,7 @@ void SlotIndexes::dump() const {
// Print a SlotIndex to a raw_ostream. // Print a SlotIndex to a raw_ostream.
void SlotIndex::print(raw_ostream &os) const { void SlotIndex::print(raw_ostream &os) const {
if (isValid()) if (isValid())
os << entry().getIndex() << "LudS"[getSlot()]; os << entry().getIndex() << "Berd"[getSlot()];
else else
os << "invalid"; os << "invalid";
} }

4
lib/CodeGen/Spiller.cpp
View File

@ -139,7 +139,7 @@ protected:
tri); tri);
MachineInstr *loadInstr(prior(miItr)); MachineInstr *loadInstr(prior(miItr));
SlotIndex loadIndex = SlotIndex loadIndex =
lis->InsertMachineInstrInMaps(loadInstr).getDefIndex(); lis->InsertMachineInstrInMaps(loadInstr).getRegSlot();
SlotIndex endIndex = loadIndex.getNextIndex(); SlotIndex endIndex = loadIndex.getNextIndex();
VNInfo *loadVNI = VNInfo *loadVNI =
newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator()); newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator());
@ -152,7 +152,7 @@ protected:
true, ss, trc, tri); true, ss, trc, tri);
MachineInstr *storeInstr(llvm::next(miItr)); MachineInstr *storeInstr(llvm::next(miItr));
SlotIndex storeIndex = SlotIndex storeIndex =
lis->InsertMachineInstrInMaps(storeInstr).getDefIndex(); lis->InsertMachineInstrInMaps(storeInstr).getRegSlot();
SlotIndex beginIndex = storeIndex.getPrevIndex(); SlotIndex beginIndex = storeIndex.getPrevIndex();
VNInfo *storeVNI = VNInfo *storeVNI =
newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator()); newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator());

10
lib/CodeGen/SplitKit.cpp
View File

@ -112,7 +112,7 @@ void SplitAnalysis::analyzeUses() {
I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E; I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
++I) ++I)
if (!I.getOperand().isUndef()) if (!I.getOperand().isUndef())
UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex()); UseSlots.push_back(LIS.getInstructionIndex(&*I).getRegSlot());
array_pod_sort(UseSlots.begin(), UseSlots.end()); array_pod_sort(UseSlots.begin(), UseSlots.end());
@ -421,7 +421,7 @@ VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg) CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
.addReg(Edit->getReg()); .addReg(Edit->getReg());
Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late) Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
.getDefIndex(); .getRegSlot();
++NumCopies; ++NumCopies;
} }
@ -640,7 +640,7 @@ void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n'); DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def)); forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
} else { } else {
SlotIndex Kill = LIS.getInstructionIndex(MBBI).getDefIndex(); SlotIndex Kill = LIS.getInstructionIndex(MBBI).getRegSlot();
DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI); DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
AssignI.setStop(Kill); AssignI.setStop(Kill);
} }
@ -958,7 +958,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
// use the same register as the def, so just do that always. // use the same register as the def, so just do that always.
SlotIndex Idx = LIS.getInstructionIndex(MI); SlotIndex Idx = LIS.getInstructionIndex(MI);
if (MO.isDef() || MO.isUndef()) if (MO.isDef() || MO.isUndef())
Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex(); Idx = Idx.getRegSlot(MO.isEarlyClobber());
// Rewrite to the mapped register at Idx. // Rewrite to the mapped register at Idx.
unsigned RegIdx = RegAssign.lookup(Idx); unsigned RegIdx = RegAssign.lookup(Idx);
@ -981,7 +981,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
if (!Edit->getParent().liveAt(Idx)) if (!Edit->getParent().liveAt(Idx))
continue; continue;
} else } else
Idx = Idx.getUseIndex(); Idx = Idx.getRegSlot(true);
getLRCalc(RegIdx).extend(LI, Idx.getNextSlot(), LIS.getSlotIndexes(), getLRCalc(RegIdx).extend(LI, Idx.getNextSlot(), LIS.getSlotIndexes(),
&MDT, &LIS.getVNInfoAllocator()); &MDT, &LIS.getVNInfoAllocator());

8
lib/CodeGen/Splitter.cpp
View File

@ -141,7 +141,7 @@ namespace llvm {
ls.lis->InsertMachineInstrInMaps(copy); ls.lis->InsertMachineInstrInMaps(copy);
SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getDefIndex(); SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getRegSlot();
VNInfo *newVal = getNewVNI(preHeaderRange->valno); VNInfo *newVal = getNewVNI(preHeaderRange->valno);
newVal->def = copyDefIdx; newVal->def = copyDefIdx;
@ -175,7 +175,7 @@ namespace llvm {
ls.lis->InsertMachineInstrInMaps(copy); ls.lis->InsertMachineInstrInMaps(copy);
SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getDefIndex(); SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getRegSlot();
// Blow away output range definition. // Blow away output range definition.
outRange->valno->def = ls.lis->getInvalidIndex(); outRange->valno->def = ls.lis->getInvalidIndex();
@ -216,13 +216,13 @@ namespace llvm {
SlotIndex instrIdx = ls.lis->getInstructionIndex(&instr); SlotIndex instrIdx = ls.lis->getInstructionIndex(&instr);
if (instr.modifiesRegister(li.reg, 0)) { if (instr.modifiesRegister(li.reg, 0)) {
LiveRange *defRange = LiveRange *defRange =
li.getLiveRangeContaining(instrIdx.getDefIndex()); li.getLiveRangeContaining(instrIdx.getRegSlot());
if (defRange != 0) // May have caught this already. if (defRange != 0) // May have caught this already.
copyRange(*defRange); copyRange(*defRange);
} }
if (instr.readsRegister(li.reg, 0)) { if (instr.readsRegister(li.reg, 0)) {
LiveRange *useRange = LiveRange *useRange =
li.getLiveRangeContaining(instrIdx.getUseIndex()); li.getLiveRangeContaining(instrIdx.getRegSlot(true));
if (useRange != 0) { // May have caught this already. if (useRange != 0) { // May have caught this already.
copyRange(*useRange); copyRange(*useRange);
} }

14
lib/CodeGen/StrongPHIElimination.cpp
View File

@ -390,7 +390,7 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &MF) {
MachineOperand *LastUse = findLastUse(MBB, SrcReg); MachineOperand *LastUse = findLastUse(MBB, SrcReg);
assert(LastUse); assert(LastUse);
SlotIndex LastUseIndex = LI->getInstructionIndex(LastUse->getParent()); SlotIndex LastUseIndex = LI->getInstructionIndex(LastUse->getParent());
SrcLI.removeRange(LastUseIndex.getDefIndex(), LI->getMBBEndIdx(MBB)); SrcLI.removeRange(LastUseIndex.getRegSlot(), LI->getMBBEndIdx(MBB));
LastUse->setIsKill(true); LastUse->setIsKill(true);
} }
@ -745,7 +745,7 @@ void StrongPHIElimination::InsertCopiesForPHI(MachineInstr *PHI,
// Set the phi-def flag for the VN at this PHI. // Set the phi-def flag for the VN at this PHI.
SlotIndex PHIIndex = LI->getInstructionIndex(PHI); SlotIndex PHIIndex = LI->getInstructionIndex(PHI);
VNInfo *DestVNI = DestLI.getVNInfoAt(PHIIndex.getDefIndex()); VNInfo *DestVNI = DestLI.getVNInfoAt(PHIIndex.getRegSlot());
assert(DestVNI); assert(DestVNI);
DestVNI->setIsPHIDef(true); DestVNI->setIsPHIDef(true);
@ -756,7 +756,7 @@ void StrongPHIElimination::InsertCopiesForPHI(MachineInstr *PHI,
SlotIndex MBBStartIndex = LI->getMBBStartIdx(MBB); SlotIndex MBBStartIndex = LI->getMBBStartIdx(MBB);
DestVNI->def = MBBStartIndex; DestVNI->def = MBBStartIndex;
DestLI.addRange(LiveRange(MBBStartIndex, DestLI.addRange(LiveRange(MBBStartIndex,
PHIIndex.getDefIndex(), PHIIndex.getRegSlot(),
DestVNI)); DestVNI));
return; return;
} }
@ -783,18 +783,18 @@ void StrongPHIElimination::InsertCopiesForPHI(MachineInstr *PHI,
LI->getVNInfoAllocator()); LI->getVNInfoAllocator());
CopyVNI->setIsPHIDef(true); CopyVNI->setIsPHIDef(true);
CopyLI.addRange(LiveRange(MBBStartIndex, CopyLI.addRange(LiveRange(MBBStartIndex,
DestCopyIndex.getDefIndex(), DestCopyIndex.getRegSlot(),
CopyVNI)); CopyVNI));
// Adjust DestReg's live interval to adjust for its new definition at // Adjust DestReg's live interval to adjust for its new definition at
// CopyInstr. // CopyInstr.
LiveInterval &DestLI = LI->getOrCreateInterval(DestReg); LiveInterval &DestLI = LI->getOrCreateInterval(DestReg);
SlotIndex PHIIndex = LI->getInstructionIndex(PHI); SlotIndex PHIIndex = LI->getInstructionIndex(PHI);
DestLI.removeRange(PHIIndex.getDefIndex(), DestCopyIndex.getDefIndex()); DestLI.removeRange(PHIIndex.getRegSlot(), DestCopyIndex.getRegSlot());
VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getDefIndex()); VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
assert(DestVNI); assert(DestVNI);
DestVNI->def = DestCopyIndex.getDefIndex(); DestVNI->def = DestCopyIndex.getRegSlot();
InsertedDestCopies[CopyReg] = CopyInstr; InsertedDestCopies[CopyReg] = CopyInstr;
} }