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add a mayLoad property for machine instructions, a correlary to mayStore.
This is currently not set by anything. llvm-svn: 45748
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6f28b87039
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@ -90,6 +90,7 @@ namespace TID {
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NotDuplicable,
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DelaySlot,
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SimpleLoad,
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MayLoad,
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MayStore,
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NeverHasSideEffects,
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MayHaveSideEffects,
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@ -308,6 +309,14 @@ public:
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//===--------------------------------------------------------------------===//
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// Side Effect Analysis
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//===--------------------------------------------------------------------===//
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/// mayLoad - Return true if this instruction could possibly read memory.
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/// Instructions with this flag set are not necessarily simple load
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/// instructions, they may load a value and modify it, for example.
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bool mayLoad() const {
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return Flags & (1 << TID::MayLoad);
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}
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/// mayStore - Return true if this instruction could possibly modify memory.
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/// Instructions with this flag set are not necessarily simple store
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@ -317,8 +326,6 @@ public:
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return Flags & (1 << TID::MayStore);
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}
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// TODO: mayLoad.
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/// hasNoSideEffects - Return true if all instances of this instruction are
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/// guaranteed to have no side effects other than:
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/// 1. The register operands that are def/used by the MachineInstr.
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@ -84,6 +84,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
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isBarrier = R->getValueAsBit("isBarrier");
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isCall = R->getValueAsBit("isCall");
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isSimpleLoad = R->getValueAsBit("isSimpleLoad");
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mayLoad = R->getValueAsBit("mayLoad");
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mayStore = R->getValueAsBit("mayStore");
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isImplicitDef= R->getValueAsBit("isImplicitDef");
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bool isTwoAddress = R->getValueAsBit("isTwoAddress");
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@ -90,7 +90,7 @@ namespace llvm {
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bool isBarrier;
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bool isCall;
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bool isSimpleLoad;
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bool mayStore;
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bool mayLoad, mayStore;
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bool isImplicitDef;
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bool isPredicable;
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bool isConvertibleToThreeAddress;
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@ -144,12 +144,12 @@ void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
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class InstAnalyzer {
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const CodeGenDAGPatterns &CDP;
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bool &mayStore;
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bool &isLoad;
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bool &mayLoad;
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bool &NeverHasSideEffects;
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public:
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InstAnalyzer(const CodeGenDAGPatterns &cdp,
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bool &maystore, bool &isload, bool &nhse)
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: CDP(cdp), mayStore(maystore), isLoad(isload), NeverHasSideEffects(nhse) {
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bool &maystore, bool &mayload, bool &nhse)
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: CDP(cdp), mayStore(maystore), mayLoad(mayload), NeverHasSideEffects(nhse){
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}
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void Analyze(Record *InstRecord) {
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@ -166,9 +166,8 @@ public:
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private:
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void AnalyzeNode(const TreePatternNode *N) {
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if (N->isLeaf()) {
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if (N->isLeaf())
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return;
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}
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if (N->getOperator()->getName() != "set") {
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// Get information about the SDNode for the operator.
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@ -191,11 +190,11 @@ private:
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};
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void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
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bool &mayStore, bool &isLoad,
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bool &mayStore, bool &mayLoad,
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bool &NeverHasSideEffects) {
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mayStore = isLoad = NeverHasSideEffects = false;
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mayStore = mayLoad = NeverHasSideEffects = false;
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InstAnalyzer(CDP, mayStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
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InstAnalyzer(CDP, mayStore, mayLoad,NeverHasSideEffects).Analyze(Inst.TheDef);
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// InstAnalyzer only correctly analyzes mayStore so far.
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if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it.
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@ -210,7 +209,7 @@ void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
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}
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// These two override everything.
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isLoad = Inst.isSimpleLoad;
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mayLoad = Inst.mayLoad;
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NeverHasSideEffects = Inst.neverHasSideEffects;
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#if 0
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@ -281,8 +280,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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const OperandInfoMapTy &OpInfo,
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std::ostream &OS) {
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// Determine properties of the instruction from its pattern.
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bool mayStore, isSimpleLoad, NeverHasSideEffects;
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InferFromPattern(Inst, mayStore, isSimpleLoad, NeverHasSideEffects);
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bool mayStore, mayLoad, NeverHasSideEffects;
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InferFromPattern(Inst, mayStore, mayLoad, NeverHasSideEffects);
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if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
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std::cerr << "error: Instruction '" << Inst.TheDef->getName()
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@ -308,7 +307,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
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if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
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if (Inst.isCall) OS << "|(1<<TID::Call)";
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if (isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
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if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
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if (mayLoad) OS << "|(1<<TID::MayLoad)";
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if (mayStore) OS << "|(1<<TID::MayStore)";
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if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
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if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
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