RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 21:00:29 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Support for i1 XOR in FastISel. It is actually safe because

Browse Source 
i1 operands are assumed to already by zero-extended.

llvm-svn: 56615
This commit is contained in:
Dan Gohman 2008-09-25 17:22:52 +00:00
parent 51cd436ad8
commit 9bb92ce6e9
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -135,10 +135,11 @@ bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
// under the assumption that i64 won't be used if the target doesn't
// support it.
if (!TLI.isTypeLegal(VT)) {
// MVT::i1 is special. Allow AND and OR (but not XOR) because they
// MVT::i1 is special. Allow AND, OR, or XOR because they
// don't require additional zeroing, which makes them easy.
if (VT == MVT::i1 &&
(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR))
(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
ISDOpcode == ISD::XOR))
VT = TLI.getTypeToTransformTo(VT);
else
return false;