RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-14 17:28:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[SystemZ] Tweak instruction format classifications

Browse Source 
There's no real need to have Shift as a separate format type from Binary.
The comments for other format types were too specific and in some cases
no longer accurate.

Just a clean-up, no behavioral change intended.

llvm-svn: 212707
This commit is contained in:
Richard Sandiford 2014-07-10 11:29:23 +00:00
parent b0b7a4016c
commit 9bea71208f
2 changed files with 43 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
lib/Target/SystemZ/SystemZInstrFormats.td
View File

@ -511,34 +511,24 @@ class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
// to store. Other stored registers are added as implicit uses.
//
// Unary:
// One register output operand and one input operand. The input
// operand may be a register, immediate or memory.
// One register output operand and one input operand.
//
// Binary:
// One register output operand and two input operands. The first
// input operand is always a register and the second may be a register,
// immediate or memory.
//
// Shift:
// One register output operand and two input operands. The first
// input operand is a register and the second has the same form as
// an address (although it isn't actually used to address memory).
// One register output operand and two input operands.
//
// Compare:
// Two input operands. The first operand is always a register,
// the second may be a register, immediate or memory.
// Two input operands and an implicit CC output operand.
//
// Ternary:
// One register output operand and three register input operands.
// One register output operand and three input operands.
//
// LoadAndOp:
// One output operand and two input operands. The first input operand
// is a register and the second is an address.
// One output operand and two input operands, one of which is an address.
// The instruction both reads from and writes to the address.
//
// CmpSwap:
// One output operand and three input operands. The first two
// operands are registers and the third is an address. The instruction
// both reads from and writes to the address.
// One output operand and three input operands, one of which is an address.
// The instruction both reads from and writes to the address.
//
// RotateSelect:
// One output operand and five input operands. The first two operands
@ -993,6 +983,33 @@ class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
let DisableEncoding = "$R1src";
}
class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls>
: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
mnemonic#"\t$R1, $BD2",
[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
let R3 = 0;
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
}
class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls>
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
mnemonic#"\t$R1, $R3, $BD2",
[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
SDPatternOperator operator, RegisterOperand cls> {
let NumOpsKey = mnemonic in {
let NumOpsValue = "3" in
def K : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
Requires<[FeatureDistinctOps]>;
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
}
}
class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
AddressingMode mode = bdxaddr12only>
@ -1077,33 +1094,6 @@ multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
}
}
class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls>
: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
mnemonic#"\t$R1, $BD2",
[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
let R3 = 0;
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
}
class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls>
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
mnemonic#"\t$R1, $R3, $BD2",
[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
multiclass ShiftRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
SDPatternOperator operator, RegisterOperand cls> {
let NumOpsKey = mnemonic in {
let NumOpsValue = "3" in
def K : ShiftRSY<mnemonic##"k", opcode2, null_frag, cls>,
Requires<[FeatureDistinctOps]>;
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
def "" : ShiftRS<mnemonic, opcode1, operator, cls>;
}
}
class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),

16
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -1015,26 +1015,26 @@ def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
// Shift left.
let neverHasSideEffects = 1 in {
defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
}
// Logical shift right.
let neverHasSideEffects = 1 in {
defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
}
// Arithmetic shift right.
let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>;
}
// Rotate left.
let neverHasSideEffects = 1 in {
def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>;
def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>;
def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
}
// Rotate second operand left and inserted selected bits into first operand.