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XCore target: Enable frames larger than 65535 to be lowered
llvm-svn: 196084
This commit is contained in:
Robert Lytton
parent
e71e08d007
commit
9c8a9af745
@ -29,6 +29,9 @@
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using namespace llvm;
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static const unsigned FramePtr = XCore::R10;
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static const int MaxImmU16 = (1<<16) - 1;
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// helper functions. FIXME: Eliminate.
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static inline bool isImmU6(unsigned val) {
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return val < (1 << 6);
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@ -38,34 +41,93 @@ static inline bool isImmU16(unsigned val) {
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return val < (1 << 16);
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}
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static void loadFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, int Offset, DebugLoc dl,
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const TargetInstrInfo &TII) {
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assert(Offset%4 == 0 && "Misaligned stack offset");
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Offset/=4;
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bool isU6 = isImmU6(Offset);
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if (!isU6 && !isImmU16(Offset))
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report_fatal_error("loadFromStack offset too big " + Twine(Offset));
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int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
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.addImm(Offset);
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static void EmitDefCfaRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc dl,
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const TargetInstrInfo &TII,
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MachineModuleInfo *MMI, unsigned DRegNum) {
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MCSymbol *Label = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(Label);
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MMI->addFrameInst(MCCFIInstruction::createDefCfaRegister(Label, DRegNum));
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}
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static void EmitDefCfaOffset(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc dl,
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const TargetInstrInfo &TII,
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MachineModuleInfo *MMI, int Offset) {
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MCSymbol *Label = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(Label);
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MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(Label, -Offset));
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}
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static void storeToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg, int Offset, DebugLoc dl,
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const TargetInstrInfo &TII) {
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assert(Offset%4 == 0 && "Misaligned stack offset");
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Offset/=4;
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bool isU6 = isImmU6(Offset);
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if (!isU6 && !isImmU16(Offset))
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report_fatal_error("storeToStack offset too big " + Twine(Offset));
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int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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BuildMI(MBB, I, dl, TII.get(Opcode))
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.addReg(SrcReg)
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.addImm(Offset);
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static void EmitCfiOffset(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc dl,
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const TargetInstrInfo &TII, MachineModuleInfo *MMI,
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unsigned DRegNum, int Offset, MCSymbol *Label) {
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if (!Label) {
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Label = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(Label);
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}
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MMI->addFrameInst(MCCFIInstruction::createOffset(Label, DRegNum, Offset));
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}
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/// The SP register is moved in steps of 'MaxImmU16' towards the bottom of the
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/// frame. During these steps, it may be necessary to spill registers.
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/// IfNeededExtSP emits the necessary EXTSP instructions to move the SP only
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/// as far as to make 'OffsetFromBottom' reachable using an STWSP_lru6.
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/// \param OffsetFromTop the spill offset from the top of the frame.
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/// \param [in] [out] Adjusted the current SP offset from the top of the frame.
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static void IfNeededExtSP(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc dl,
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const TargetInstrInfo &TII, MachineModuleInfo *MMI,
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int OffsetFromTop, int &Adjusted, int FrameSize,
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bool emitFrameMoves) {
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while (OffsetFromTop > Adjusted) {
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assert(Adjusted < FrameSize && "OffsetFromTop is beyond FrameSize");
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int remaining = FrameSize - Adjusted;
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int OpImm = (remaining > MaxImmU16) ? MaxImmU16 : remaining;
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int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
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Adjusted += OpImm;
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if (emitFrameMoves)
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EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
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}
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}
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/// The SP register is moved in steps of 'MaxImmU16' towards the top of the
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/// frame. During these steps, it may be necessary to re-load registers.
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/// IfNeededLDAWSP emits the necessary LDAWSP instructions to move the SP only
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/// as far as to make 'OffsetFromTop' reachable using an LDAWSP_lru6.
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/// \param OffsetFromTop the spill offset from the top of the frame.
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/// \param [in] [out] RemainingAdj the current SP offset from the top of the frame.
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static void IfNeededLDAWSP(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc dl,
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const TargetInstrInfo &TII, int OffsetFromTop,
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int &RemainingAdj) {
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while (OffsetFromTop < RemainingAdj - MaxImmU16) {
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assert(RemainingAdj && "OffsetFromTop is beyond FrameSize");
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int OpImm = (RemainingAdj > MaxImmU16) ? MaxImmU16 : RemainingAdj;
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int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
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RemainingAdj -= OpImm;
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}
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}
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/// Creates an ordered list of registers that are spilled
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/// during the emitPrologue/emitEpilogue.
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/// Registers are ordered according to their frame offset.
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static void GetSpillList(SmallVectorImpl<std::pair<unsigned,int> > &SpillList,
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MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
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bool fetchLR, bool fetchFP) {
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int LRSpillOffset = fetchLR? MFI->getObjectOffset(XFI->getLRSpillSlot()) : 0;
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int FPSpillOffset = fetchFP? MFI->getObjectOffset(XFI->getFPSpillSlot()) : 0;
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if (fetchLR && fetchFP && LRSpillOffset > FPSpillOffset) {
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SpillList.push_back(std::make_pair<unsigned,int>(XCore::LR,LRSpillOffset));
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fetchLR = false;
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}
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if (fetchFP)
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SpillList.push_back(std::make_pair<unsigned,int>(FramePtr, FPSpillOffset));
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if (fetchLR)
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SpillList.push_back(std::make_pair<unsigned,int>(XCore::LR,LRSpillOffset));
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}
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@ -80,7 +142,7 @@ XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
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bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MF.getFrameInfo()->hasVarSizedObjects();
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MF.getFrameInfo()->hasVarSizedObjects();
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}
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void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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@ -98,90 +160,69 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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report_fatal_error("emitPrologue unsupported alignment: "
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+ Twine(MFI->getMaxAlignment()));
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bool FP = hasFP(MF);
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const AttributeSet &PAL = MF.getFunction()->getAttributes();
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if (PAL.hasAttrSomewhere(Attribute::Nest))
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loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
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BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
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// Work out frame sizes.
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int FrameSize = MFI->getStackSize();
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assert(FrameSize%4 == 0 && "Misaligned frame size");
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FrameSize/=4;
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bool isU6 = isImmU6(FrameSize);
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if (!isU6 && !isImmU16(FrameSize)) {
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// FIXME could emit multiple instructions.
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report_fatal_error("emitPrologue Frame size too big: " + Twine(FrameSize));
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}
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bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF);
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// We will adjust the SP in stages towards the final FrameSize.
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assert(MFI->getStackSize()%4 == 0 && "Misaligned frame size");
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const int FrameSize = MFI->getStackSize() / 4;
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int Adjusted = 0;
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bool saveLR = XFI->getUsesLR();
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// Do we need to allocate space on the stack?
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if (FrameSize) {
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bool LRSavedOnEntry = false;
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int Opcode;
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if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
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Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
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MBB.addLiveIn(XCore::LR);
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saveLR = false;
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LRSavedOnEntry = true;
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} else {
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Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
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}
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BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
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bool UseENTSP = saveLR && FrameSize
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&& (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
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if (UseENTSP)
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saveLR = false;
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bool FP = hasFP(MF);
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bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF);
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if (emitFrameMoves) {
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// Show update of SP.
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MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
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MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(FrameLabel,
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-FrameSize*4));
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if (LRSavedOnEntry) {
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unsigned Reg = MRI->getDwarfRegNum(XCore::LR, true);
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MMI->addFrameInst(MCCFIInstruction::createOffset(FrameLabel, Reg, 0));
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}
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}
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}
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if (saveLR) {
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int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
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storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
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if (UseENTSP) {
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// Allocate space on the stack at the same time as saving LR.
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Adjusted = (FrameSize > MaxImmU16) ? MaxImmU16 : FrameSize;
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int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(Adjusted);
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MBB.addLiveIn(XCore::LR);
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if (emitFrameMoves) {
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MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
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unsigned Reg = MRI->getDwarfRegNum(XCore::LR, true);
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MMI->addFrameInst(MCCFIInstruction::createOffset(SaveLRLabel, Reg,
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LRSpillOffset));
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EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
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unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, 0, NULL);
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}
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}
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// If necessary, save LR and FP to the stack, as we EXTSP.
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SmallVector<std::pair<unsigned,int>,2> SpillList;
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GetSpillList(SpillList, MFI, XFI, saveLR, FP);
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for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
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unsigned SpillReg = SpillList[i].first;
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int SpillOffset = SpillList[i].second;
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assert(SpillOffset % 4 == 0 && "Misaligned stack offset");
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assert(SpillOffset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillOffset/4;
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IfNeededExtSP(MBB, MBBI, dl, TII, MMI, OffsetFromTop, Adjusted, FrameSize,
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emitFrameMoves);
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int Offset = Adjusted - OffsetFromTop;
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int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addReg(SpillReg).addImm(Offset);
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MBB.addLiveIn(SpillReg);
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if (emitFrameMoves) {
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unsigned DRegNum = MRI->getDwarfRegNum(SpillReg, true);
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, SpillOffset, NULL);
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}
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}
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// Complete any remaining Stack adjustment.
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IfNeededExtSP(MBB, MBBI, dl, TII, MMI, FrameSize, Adjusted, FrameSize,
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emitFrameMoves);
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assert(Adjusted==FrameSize && "IfNeededExtSP has not completed adjustment");
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if (FP) {
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// Save R10 to the stack.
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int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
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storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII);
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// R10 is live-in. It is killed at the spill.
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MBB.addLiveIn(XCore::R10);
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if (emitFrameMoves) {
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MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
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unsigned Reg = MRI->getDwarfRegNum(XCore::R10, true);
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MMI->addFrameInst(MCCFIInstruction::createOffset(SaveR10Label, Reg,
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FPSpillOffset));
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}
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// Set the FP from the SP.
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unsigned FramePtr = XCore::R10;
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BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
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if (emitFrameMoves) {
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// Show FP is now valid.
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MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
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unsigned Reg = MRI->getDwarfRegNum(FramePtr, true);
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MMI->addFrameInst(MCCFIInstruction::createDefCfaRegister(FrameLabel,
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Reg));
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}
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if (emitFrameMoves)
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EmitDefCfaRegister(MBB, MBBI, dl, TII, MMI,
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MRI->getDwarfRegNum(FramePtr, true));
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}
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if (emitFrameMoves) {
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@ -192,9 +233,8 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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MCSymbol *SpillLabel = SpillLabels[I].first;
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CalleeSavedInfo &CSI = SpillLabels[I].second;
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int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
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unsigned Reg = MRI->getDwarfRegNum(CSI.getReg(), true);
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MMI->addFrameInst(MCCFIInstruction::createOffset(SpillLabel, Reg,
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Offset));
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unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, Offset, SpillLabel);
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}
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}
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}
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@ -208,60 +248,58 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
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XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
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DebugLoc dl = MBBI->getDebugLoc();
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bool FP = hasFP(MF);
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if (FP) {
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// Restore the stack pointer.
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unsigned FramePtr = XCore::R10;
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BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
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.addReg(FramePtr);
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}
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// Work out frame sizes.
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int FrameSize = MFI->getStackSize();
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assert(FrameSize%4 == 0 && "Misaligned frame size");
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FrameSize/=4;
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bool isU6 = isImmU6(FrameSize);
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if (!isU6 && !isImmU16(FrameSize)) {
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// FIXME could emit multiple instructions.
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report_fatal_error("emitEpilogue Frame size too big: " + Twine(FrameSize));
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}
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if (FP) {
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// Restore R10
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int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
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FPSpillOffset += FrameSize*4;
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loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII);
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}
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// We will adjust the SP in stages towards the final FrameSize.
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int RemainingAdj = MFI->getStackSize();
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assert(RemainingAdj%4 == 0 && "Misaligned frame size");
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RemainingAdj /= 4;
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bool restoreLR = XFI->getUsesLR();
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if (restoreLR &&
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(FrameSize == 0 || MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0)) {
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int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
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LRSpillOffset += FrameSize*4;
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loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII);
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bool UseRETSP = restoreLR && RemainingAdj
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&& (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
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if (UseRETSP)
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restoreLR = false;
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bool FP = hasFP(MF);
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if (FP) // Restore the stack pointer.
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BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
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// If necessary, restore LR and FP from the stack, as we EXTSP.
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SmallVector<std::pair<unsigned,int>,2> SpillList;
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GetSpillList(SpillList, MFI, XFI, restoreLR, FP);
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unsigned i = SpillList.size();
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while (i--) {
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unsigned SpilledReg = SpillList[i].first;
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int SpillOffset = SpillList[i].second;
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assert(SpillOffset % 4 == 0 && "Misaligned stack offset");
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assert(SpillOffset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillOffset/4;
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IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
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int Offset = RemainingAdj - OffsetFromTop;
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int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpilledReg).addImm(Offset);
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}
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if (FrameSize) {
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if (restoreLR) {
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if (RemainingAdj) {
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// Complete all but one of the remaining Stack adjustments.
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IfNeededLDAWSP(MBB, MBBI, dl, TII, 0, RemainingAdj);
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if (UseRETSP) {
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// Fold prologue into return instruction
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assert(MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
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assert(MBBI->getOpcode() == XCore::RETSP_u6
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|| MBBI->getOpcode() == XCore::RETSP_lu6);
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int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
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|| MBBI->getOpcode() == XCore::RETSP_lu6);
|
||||
int Opcode = isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
|
||||
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
|
||||
.addImm(RemainingAdj);
|
||||
for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i)
|
||||
MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
|
||||
MBB.erase(MBBI);
|
||||
MBB.erase(MBBI); // Erase the previous return instruction.
|
||||
} else {
|
||||
int Opcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
|
||||
BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
|
||||
int Opcode = isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 :
|
||||
XCore::LDAWSP_lru6;
|
||||
BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);
|
||||
// Don't erase the return instruction.
|
||||
}
|
||||
}
|
||||
} // else Don't erase the return instruction.
|
||||
}
|
||||
|
||||
bool XCoreFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
@ -278,7 +316,8 @@ bool XCoreFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
|
||||
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
if (MI != MBB.end())
|
||||
DL = MI->getDebugLoc();
|
||||
|
||||
for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
|
||||
it != CSI.end(); ++it) {
|
||||
|
||||
@ -1,5 +1,15 @@
|
||||
; RUN: llc < %s -march=xcore | FileCheck %s
|
||||
; RUN: llc < %s -march=xcore -disable-fp-elim | FileCheck %s -check-prefix=CHECKFP
|
||||
|
||||
|
||||
; CHECKFP-LABEL: f1
|
||||
; CHECKFP: entsp 2
|
||||
; CHECKFP-NEXT: stw r10, sp[1]
|
||||
; CHECKFP-NEXT: ldaw r10, sp[0]
|
||||
; CHECKFP: set sp, r10
|
||||
; CHECKFP-NEXT: ldw r10, sp[1]
|
||||
; CHECKFP-NEXT: retsp 2
|
||||
;
|
||||
; CHECK-LABEL: f1
|
||||
; CHECK: stw lr, sp[0]
|
||||
; CHECK: ldw lr, sp[0]
|
||||
@ -10,6 +20,22 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; CHECKFP-LABEL:f3
|
||||
; CHECKFP: entsp 3
|
||||
; CHECKFP-NEXT: stw r10, sp[1]
|
||||
; CHECKFP-NEXT: ldaw r10, sp[0]
|
||||
; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[2]
|
||||
; CHECKFP-NEXT: mov [[REG]], r0
|
||||
; CHECKFP-NEXT: extsp 1
|
||||
; CHECKFP-NEXT: bl f2
|
||||
; CHECKFP-NEXT: ldaw sp, sp[1]
|
||||
; CHECKFP-NEXT: mov r0, [[REG]]
|
||||
; CHECKFP-NEXT: ldw [[REG]], r10[2]
|
||||
; CHECKFP-NEXT: set sp, r10
|
||||
; CHECKFP-NEXT: ldw r10, sp[1]
|
||||
; CHECKFP-NEXT: retsp 3
|
||||
;
|
||||
; CHECK-LABEL: f3
|
||||
; CHECK: entsp 2
|
||||
; CHECK: stw [[REG:r[4-9]+]], sp[1]
|
||||
@ -24,3 +50,102 @@ entry:
|
||||
call void @f2()
|
||||
ret i32 %i
|
||||
}
|
||||
|
||||
|
||||
; CHECKFP-LABEL: f4
|
||||
; CHECKFP: extsp 65535
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
|
||||
; CHECKFP-NEXT: extsp 34467
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_def_cfa_offset 400008
|
||||
; CHECKFP-NEXT: stw r10, sp[1]
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_offset 10, -400004
|
||||
; CHECKFP-NEXT: ldaw r10, sp[0]
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_def_cfa_register 10
|
||||
; CHECKFP-NEXT: set sp, r10
|
||||
; CHECKFP-NEXT: ldw r10, sp[1]
|
||||
; CHECKFP-NEXT: ldaw sp, sp[65535]
|
||||
; CHECKFP-NEXT: ldaw sp, sp[34467]
|
||||
; CHECKFP-NEXT: retsp 0
|
||||
;
|
||||
; CHECK-LABEL: f4
|
||||
; CHECK: extsp 65535
|
||||
; CHECK-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 262140
|
||||
; CHECK-NEXT: extsp 34465
|
||||
; CHECK-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 400000
|
||||
; CHECK-NEXT: ldaw sp, sp[65535]
|
||||
; CHECK-NEXT: ldaw sp, sp[34465]
|
||||
; CHECK-NEXT: retsp 0
|
||||
define void @f4() {
|
||||
entry:
|
||||
%0 = alloca [100000 x i32], align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; CHECKFP-LABEL: f6
|
||||
; CHECKFP: entsp 65535
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_offset 15, 0
|
||||
; CHECKFP-NEXT: extsp 65535
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_def_cfa_offset 524280
|
||||
; CHECKFP-NEXT: extsp 65535
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_def_cfa_offset 786420
|
||||
; CHECKFP-NEXT: extsp 3396
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_def_cfa_offset 800004
|
||||
; CHECKFP-NEXT: stw r10, sp[1]
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_offset 10, -800000
|
||||
; CHECKFP-NEXT: ldaw r10, sp[0]
|
||||
; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECKFP-NEXT: .cfi_def_cfa_register 10
|
||||
; CHECKFP-NEXT: extsp 1
|
||||
; CHECKFP-NEXT: ldaw r0, r10[2]
|
||||
; CHECKFP-NEXT: bl f5
|
||||
; CHECKFP-NEXT: ldaw sp, sp[1]
|
||||
; CHECKFP-NEXT: set sp, r10
|
||||
; CHECKFP-NEXT: ldw r10, sp[1]
|
||||
; CHECKFP-NEXT: ldaw sp, sp[65535]
|
||||
; CHECKFP-NEXT: ldaw sp, sp[65535]
|
||||
; CHECKFP-NEXT: ldaw sp, sp[65535]
|
||||
; CHECKFP-NEXT: retsp 3396
|
||||
;
|
||||
; CHECK-LABEL: f6
|
||||
; CHECK: entsp 65535
|
||||
; CHECK-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 262140
|
||||
; CHECK-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECK-NEXT: .cfi_offset 15, 0
|
||||
; CHECK-NEXT: extsp 65535
|
||||
; CHECK-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 524280
|
||||
; CHECK-NEXT: extsp 65535
|
||||
; CHECK-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 786420
|
||||
; CHECK-NEXT: extsp 3395
|
||||
; CHECK-NEXT: .Ltmp{{[0-9]+}}
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 800000
|
||||
; CHECK-NEXT: ldaw r0, sp[1]
|
||||
; CHECK-NEXT: bl f5
|
||||
; CHECK-NEXT: ldaw sp, sp[65535]
|
||||
; CHECK-NEXT: ldaw sp, sp[65535]
|
||||
; CHECK-NEXT: ldaw sp, sp[65535]
|
||||
; CHECK-NEXT: retsp 3395
|
||||
declare void @f5(i32*)
|
||||
define void @f6() {
|
||||
entry:
|
||||
%0 = alloca [199999 x i32], align 4
|
||||
%1 = getelementptr inbounds [199999 x i32]* %0, i32 0, i32 0
|
||||
call void @f5(i32* %1)
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user