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[ARM] Add support for the MVE long shift instructions
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers. The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl. test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions. Differential Revision: https://reviews.llvm.org/D63430 llvm-svn: 364654
This commit is contained in:
Sam Tebbs
parent
33e65f7a8d
commit
9cb186cbd7
@ -932,6 +932,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SRA, MVT::i64, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
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// MVE lowers 64 bit shifts to lsll and lsrl
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// assuming that ISD::SRL and SRA of i64 are already marked custom
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if (Subtarget->hasMVEIntegerOps())
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setOperationAction(ISD::SHL, MVT::i64, Custom);
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// Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
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if (Subtarget->isThumb1Only()) {
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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@ -1411,6 +1416,10 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::SSAT: return "ARMISD::SSAT";
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case ARMISD::USAT: return "ARMISD::USAT";
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case ARMISD::ASRL: return "ARMISD::ASRL";
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case ARMISD::LSRL: return "ARMISD::LSRL";
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case ARMISD::LSLL: return "ARMISD::LSLL";
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case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
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case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
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case ARMISD::RRX: return "ARMISD::RRX";
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@ -5619,11 +5628,54 @@ static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
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if (VT != MVT::i64)
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return SDValue();
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assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
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assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
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N->getOpcode() == ISD::SHL) &&
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"Unknown shift to lower!");
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unsigned ShOpc = N->getOpcode();
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if (ST->hasMVEIntegerOps()) {
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SDValue ShAmt = N->getOperand(1);
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unsigned ShPartsOpc = ARMISD::LSLL;
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ConstantSDNode *Con = dyn_cast<ConstantSDNode>(ShAmt);
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// If the shift amount is greater than 32 then do the default optimisation
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if (Con && Con->getZExtValue() > 32)
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return SDValue();
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// Extract the lower 32 bits of the shift amount if it's an i64
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if (ShAmt->getValueType(0) == MVT::i64)
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ShAmt = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ShAmt,
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DAG.getConstant(0, dl, MVT::i32));
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if (ShOpc == ISD::SRL) {
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if (!Con)
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// There is no t2LSRLr instruction so negate and perform an lsll if the
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// shift amount is in a register, emulating a right shift.
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ShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
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DAG.getConstant(0, dl, MVT::i32), ShAmt);
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else
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// Else generate an lsrl on the immediate shift amount
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ShPartsOpc = ARMISD::LSRL;
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} else if (ShOpc == ISD::SRA)
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ShPartsOpc = ARMISD::ASRL;
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// Lower 32 bits of the destination/source
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SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
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DAG.getConstant(0, dl, MVT::i32));
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// Upper 32 bits of the destination/source
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SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
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DAG.getConstant(1, dl, MVT::i32));
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// Generate the shift operation as computed above
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Lo = DAG.getNode(ShPartsOpc, dl, DAG.getVTList(MVT::i32, MVT::i32), Lo, Hi,
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ShAmt);
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// The upper 32 bits come from the second return value of lsll
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Hi = SDValue(Lo.getNode(), 1);
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return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
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}
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// We only lower SRA, SRL of 1 here, all others use generic lowering.
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if (!isOneConstant(N->getOperand(1)))
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if (!isOneConstant(N->getOperand(1)) || N->getOpcode() == ISD::SHL)
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return SDValue();
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// If we are in thumb mode, we don't have RRX.
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@ -8291,6 +8343,7 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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break;
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case ISD::SRL:
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case ISD::SRA:
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case ISD::SHL:
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Res = Expand64BitShift(N, DAG, Subtarget);
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break;
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case ISD::SREM:
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@ -76,6 +76,10 @@ class VectorType;
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PIC_ADD, // Add with a PC operand and a PIC label.
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ASRL, // MVE long arithmetic shift right.
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LSRL, // MVE long shift right.
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LSLL, // MVE long shift left.
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CMP, // ARM compare instructions.
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CMN, // ARM CMN instructions.
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CMPZ, // ARM compare that sets only Z flag.
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@ -99,6 +99,13 @@ def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>,
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SDTCisSameAs<0, 4>,
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SDTCisSameAs<0, 5>]>;
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// ARMlsll, ARMlsrl, ARMasrl
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def SDT_ARMIntShiftParts : SDTypeProfile<2, 3, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisSameAs<0, 3>,
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SDTCisInt<0>,
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SDTCisInt<4>]>;
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def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>;
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def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>;
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def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>;
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@ -171,6 +178,10 @@ def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
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def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
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def ARMasrl : SDNode<"ARMISD::ASRL", SDT_ARMIntShiftParts, []>;
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def ARMlsrl : SDNode<"ARMISD::LSRL", SDT_ARMIntShiftParts, []>;
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def ARMlsll : SDNode<"ARMISD::LSLL", SDT_ARMIntShiftParts, []>;
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def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
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def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
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def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
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@ -427,11 +427,21 @@ class MVE_ScalarShiftDRegReg<string iname, bit op5, bit op16,
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let DecoderMethod = "DecodeMVEOverlappingLongShift";
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}
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def MVE_ASRLr : MVE_ScalarShiftDRegReg<"asrl", 0b1, 0b0>;
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def MVE_ASRLi : MVE_ScalarShiftDRegImm<"asrl", 0b10, ?>;
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def MVE_LSLLr : MVE_ScalarShiftDRegReg<"lsll", 0b0, 0b0>;
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def MVE_LSLLi : MVE_ScalarShiftDRegImm<"lsll", 0b00, ?>;
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def MVE_LSRL : MVE_ScalarShiftDRegImm<"lsrl", 0b01, ?>;
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def MVE_ASRLr : MVE_ScalarShiftDRegReg<"asrl", 0b1, 0b0, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
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(ARMasrl tGPREven:$RdaLo_src,
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tGPROdd:$RdaHi_src, rGPR:$Rm))]>;
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def MVE_ASRLi : MVE_ScalarShiftDRegImm<"asrl", 0b10, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
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(ARMasrl tGPREven:$RdaLo_src,
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tGPROdd:$RdaHi_src, (i32 imm:$imm)))]>;
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def MVE_LSLLr : MVE_ScalarShiftDRegReg<"lsll", 0b0, 0b0, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
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(ARMlsll tGPREven:$RdaLo_src,
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tGPROdd:$RdaHi_src, rGPR:$Rm))]>;
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def MVE_LSLLi : MVE_ScalarShiftDRegImm<"lsll", 0b00, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
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(ARMlsll tGPREven:$RdaLo_src,
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tGPROdd:$RdaHi_src, (i32 imm:$imm)))]>;
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def MVE_LSRL : MVE_ScalarShiftDRegImm<"lsrl", 0b01, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
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(ARMlsrl tGPREven:$RdaLo_src,
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tGPROdd:$RdaHi_src, (i32 imm:$imm)))]>;
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def MVE_SQRSHRL : MVE_ScalarShiftDRegReg<"sqrshrl", 0b1, 0b1>;
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def MVE_SQSHLL : MVE_ScalarShiftDRegImm<"sqshll", 0b11, 0b1>;
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221
test/CodeGen/ARM/shift_parts.ll
Normal file
221
test/CodeGen/ARM/shift_parts.ll
Normal file
@ -0,0 +1,221 @@
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; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-MVE
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; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1-m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-NON-MVE
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define i64 @shift_left_reg(i64 %x, i64 %y) {
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; CHECK-MVE-LABEL: shift_left_reg:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsll r0, r1, r2
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_left_reg:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: .save {r7, lr}
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; CHECK-NON-MVE-NEXT: push {r7, lr}
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; CHECK-NON-MVE-NEXT: bl __aeabi_llsl
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; CHECK-NON-MVE-NEXT: pop {r7}
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; CHECK-NON-MVE-NEXT: pop {r2}
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; CHECK-NON-MVE-NEXT: bx r2
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entry:
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%shl = shl i64 %x, %y
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ret i64 %shl
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}
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define i64 @shift_left_imm(i64 %x) {
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; CHECK-MVE-LABEL: shift_left_imm:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsll r0, r1, #3
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_left_imm:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: lsrs r2, r0, #29
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; CHECK-NON-MVE-NEXT: lsls r1, r1, #3
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; CHECK-NON-MVE-NEXT: adds r1, r1, r2
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; CHECK-NON-MVE-NEXT: lsls r0, r0, #3
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shl = shl i64 %x, 3
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ret i64 %shl
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}
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define i64 @shift_left_imm_big(i64 %x) {
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; CHECK-LABEL: shift_left_imm_big:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r1, r0, #16
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: bx lr
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entry:
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%shl = shl i64 %x, 48
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ret i64 %shl
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}
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define i64 @shift_left_imm_big2(i64 %x) {
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; CHECK-MVE-LABEL: shift_left_imm_big2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsll r0, r1, #32
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_left_imm_big2:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: movs r1, r0
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; CHECK-NON-MVE-NEXT: movs r0, #0
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shl = shl i64 %x, 32
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ret i64 %shl
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}
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define i64 @shift_left_imm_big3(i64 %x) {
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; CHECK-LABEL: shift_left_imm_big3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r1, r0, #1
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: bx lr
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entry:
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%shl = shl i64 %x, 33
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ret i64 %shl
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}
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define i64 @shift_right_reg(i64 %x, i64 %y) {
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; CHECK-MVE-LABEL: shift_right_reg:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: rsbs r2, r2, #0
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; CHECK-MVE-NEXT: lsll r0, r1, r2
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_right_reg:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: .save {r7, lr}
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; CHECK-NON-MVE-NEXT: push {r7, lr}
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; CHECK-NON-MVE-NEXT: bl __aeabi_llsr
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; CHECK-NON-MVE-NEXT: pop {r7}
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; CHECK-NON-MVE-NEXT: pop {r2}
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; CHECK-NON-MVE-NEXT: bx r2
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entry:
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%shr = lshr i64 %x, %y
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ret i64 %shr
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}
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define i64 @shift_right_imm(i64 %x) {
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; CHECK-MVE-LABEL: shift_right_imm:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #3
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_right_imm:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: lsls r2, r1, #29
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; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3
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; CHECK-NON-MVE-NEXT: adds r0, r0, r2
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; CHECK-NON-MVE-NEXT: lsrs r1, r1, #3
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 3
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ret i64 %shr
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}
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define i64 @shift_right_imm_big(i64 %x) {
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; CHECK-LABEL: shift_right_imm_big:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r0, r1, #16
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 48
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ret i64 %shr
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}
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define i64 @shift_right_imm_big2(i64 %x) {
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; CHECK-MVE-LABEL: shift_right_imm_big2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #32
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_right_imm_big2:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: movs r0, r1
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; CHECK-NON-MVE-NEXT: movs r1, #0
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 32
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ret i64 %shr
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}
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define i64 @shift_right_imm_big3(i64 %x) {
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; CHECK-LABEL: shift_right_imm_big3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r0, r1, #1
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 33
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ret i64 %shr
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}
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define i64 @shift_arithmetic_right_reg(i64 %x, i64 %y) {
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; CHECK-MVE-LABEL: shift_arithmetic_right_reg:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: asrl r0, r1, r2
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_arithmetic_right_reg:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: .save {r7, lr}
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; CHECK-NON-MVE-NEXT: push {r7, lr}
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; CHECK-NON-MVE-NEXT: bl __aeabi_lasr
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; CHECK-NON-MVE-NEXT: pop {r7}
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; CHECK-NON-MVE-NEXT: pop {r2}
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; CHECK-NON-MVE-NEXT: bx r2
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entry:
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%shr = ashr i64 %x, %y
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ret i64 %shr
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}
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define i64 @shift_arithmetic_right_imm(i64 %x) {
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; CHECK-MVE-LABEL: shift_arithmetic_right_imm:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: asrl r0, r1, #3
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_arithmetic_right_imm:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: lsls r2, r1, #29
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; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3
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; CHECK-NON-MVE-NEXT: adds r0, r0, r2
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; CHECK-NON-MVE-NEXT: asrs r1, r1, #3
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shr = ashr i64 %x, 3
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ret i64 %shr
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}
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%struct.bar = type { i16, i8, [5 x i8] }
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define arm_aapcs_vfpcc void @fn1(%struct.bar* nocapture %a) {
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; CHECK-MVE-LABEL: fn1:
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; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: ldr r2, [r0, #4]
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: lsll r2, r1, #8
|
||||
; CHECK-MVE-NEXT: strb r1, [r0, #7]
|
||||
; CHECK-MVE-NEXT: str.w r2, [r0, #3]
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
;
|
||||
; CHECK-NON-MVE-LABEL: fn1:
|
||||
; CHECK-NON-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-NON-MVE-NEXT: ldr r1, [r0, #4]
|
||||
; CHECK-NON-MVE-NEXT: lsls r2, r1, #8
|
||||
; CHECK-NON-MVE-NEXT: movs r3, #3
|
||||
; CHECK-NON-MVE-NEXT: str r2, [r0, r3]
|
||||
; CHECK-NON-MVE-NEXT: adds r0, r0, #3
|
||||
; CHECK-NON-MVE-NEXT: lsrs r1, r1, #24
|
||||
; CHECK-NON-MVE-NEXT: strb r1, [r0, #4]
|
||||
; CHECK-NON-MVE-NEXT: bx lr
|
||||
entry:
|
||||
%carey = getelementptr inbounds %struct.bar, %struct.bar* %a, i32 0, i32 2
|
||||
%0 = bitcast [5 x i8]* %carey to i40*
|
||||
%bf.load = load i40, i40* %0, align 1
|
||||
%bf.clear = and i40 %bf.load, -256
|
||||
store i40 %bf.clear, i40* %0, align 1
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user