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[mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions

Browse Source 
Differential Revision: http://reviews.llvm.org/D14117

llvm-svn: 269408
This commit is contained in:
Hrvoje Varga 2016-05-13 11:32:53 +00:00
parent da6a122f1e
commit 9dc958973e
16 changed files with 113 additions and 5 deletions
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14
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@ -194,6 +194,11 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@ -1827,6 +1832,15 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
unsigned Insn,
uint64_t Address,

23
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -230,6 +230,29 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
return 0;
}
/// getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
/// target operand. If the machine operand requires relocation,
/// record the relocation and return zero.
unsigned MipsMCCodeEmitter::
getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 2.
if (MO.isImm()) return MO.getImm() >> 1;
assert(MO.isExpr() &&
"getBranchTargetOpValue expects only expressions or immediates");
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
Fixups.push_back(MCFixup::create(0, FixupExpression,
MCFixupKind(Mips::fixup_Mips_PC16)));
return 0;
}
/// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
/// target operand. If the machine operand requires relocation,
/// record the relocation and return zero.

7
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
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@ -102,6 +102,13 @@ public:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
// target operand. If the machine operand requires relocation,
// record the relocation and return zero.
unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchTarget7OpValue - Return binary encoding of the microMIPS branch
// target operand. If the machine operand requires relocation,
// record the relocation and return zero.

9
lib/Target/Mips/MicroMipsDSPInstrFormats.td
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@ -242,3 +242,12 @@ class POOL32A_5B01RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
let Inst{13-6} = op;
let Inst{5-0} = 0b111100;
}
class POOL32I_IMMB0_FMT<string opstr, bits<5> op> : MMDSPInst<opstr> {
bits<16> offset;
let Inst{31-26} = 0b010000;
let Inst{25-21} = op;
let Inst{20-16} = 0;
let Inst{15-0} = offset;
}

22
lib/Target/Mips/MicroMipsDSPInstrInfo.td
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@ -155,6 +155,11 @@ class PICK_QB_MM_ENC : POOL32A_3RB0_FMT<"pick.qb", 0b0111101101>;
class SHILO_MM_ENC : POOL32A_4B0SHIFT6AC4B0_FMT<"shilo", 0b0000011101>;
class SHILOV_MM_ENC : POOL32A_5B01RAC_FMT<"shilov", 0b01001001>;
class WRDSP_MM_ENC : POOL32A_1RMASK7_FMT<"wrdsp", 0b01011001>;
class APPEND_MMR2_ENC : POOL32A_2RSA5B0_FMT<"append", 0b1000010101>;
class MODSUB_MM_ENC : POOL32A_3RB0_FMT<"modsub", 0b1010010101>;
class MULSA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"mulsa.w.ph", 0b10110010>;
class MULSAQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"mulsaq_s.w.ph", 0b11110010>;
class BPOSGE32C_MMR3_ENC : POOL32I_IMMB0_FMT<"bposge32c", 0b11001>;
// Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
@ -368,6 +373,16 @@ class WRDSP_MM_DESC {
InstrItinClass Itinerary = NoItinerary;
}
class BPOSGE32C_MMR3_DESC {
dag OutOperandList = (outs);
dag InOperandList = (ins brtarget1SImm16:$offset);
string AsmString = !strconcat("bposge32c", "\t$offset");
InstrItinClass Itinerary = NoItinerary;
bit isBranch = 1;
bit isTerminator = 1;
bit hasDelaySlot = 0;
}
// Instruction defs.
// microMIPS DSP Rev 1
def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
@ -472,6 +487,8 @@ def PICK_QB_MM : DspMMRel, PICK_QB_MM_ENC, PICK_QB_DESC;
def SHILO_MM : DspMMRel, SHILO_MM_ENC, SHILO_DESC;
def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC;
def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC;
def MODSUB_MM : DspMMRel, MODSUB_MM_ENC, MODSUB_DESC;
def MULSAQ_S_W_PH_MM : DspMMRel, MULSAQ_S_W_PH_MM_ENC, MULSAQ_S_W_PH_DESC;
// microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2;
@ -526,3 +543,8 @@ def PREPEND_MMR2 : DspMMRel, PREPEND_MMR2_ENC, PREPEND_DESC, ISA_DSPR2;
// Instruction alias.
def : MMDSPInstAlias<"wrdsp $rt", (WRDSP_MM GPR32Opnd:$rt, 0x1F), 1>;
def APPEND_MMR2 : DspMMRel, APPEND_MMR2_ENC, APPEND_DESC, ISA_DSPR2;
def MULSA_W_PH_MMR2 : DspMMRel, MULSA_W_PH_MMR2_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
// microMIPS DSP Rev 3
def BPOSGE32C_MMR3 : DspMMRel, BPOSGE32C_MMR3_ENC, BPOSGE32C_MMR3_DESC,
ISA_DSPR3;

4
lib/Target/Mips/MipsDSPInstrFormats.td
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@ -32,6 +32,10 @@ class ISA_DSPR2 {
list<Predicate> InsnPredicates = [HasDSPR2];
}
class ISA_DSPR3 {
list<Predicate> InsnPredicates = [HasDSPR3];
}
// Fields.
class Field6<bits<6> val> {
bits<6> V = val;

10
lib/Target/Mips/MipsDSPInstrInfo.td
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@ -1115,7 +1115,7 @@ def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
def MODSUB : MODSUB_ENC, MODSUB_DESC;
def MODSUB : DspMMRel, MODSUB_ENC, MODSUB_DESC;
def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;
def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
@ -1154,7 +1154,7 @@ def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
def MULSAQ_S_W_PH : DspMMRel, MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
@ -1197,7 +1197,7 @@ def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
def LWX : DspMMRel, LWX_ENC, LWX_DESC;
def LHX : DspMMRel, LHX_ENC, LHX_DESC;
def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
def INSV : DspMMRel, INSV_ENC, INSV_DESC;
def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
@ -1253,7 +1253,7 @@ def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
def MULSA_W_PH : DspMMRel, MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2;
def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2;
def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
@ -1263,7 +1263,7 @@ def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;
def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
def APPEND : APPEND_ENC, APPEND_DESC, ISA_DSPR2;
def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;
def BALIGN : BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;

6
lib/Target/Mips/MipsInstrInfo.td
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@ -622,6 +622,12 @@ def brtarget : Operand<OtherVT> {
let DecoderMethod = "DecodeBranchTarget";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def brtarget1SImm16 : Operand<OtherVT> {
let EncoderMethod = "getBranchTargetOpValue1SImm16";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget1SImm16";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def calltarget : Operand<iPTR> {
let EncoderMethod = "getJumpTargetOpValue";
let ParserMatchClass = MipsJumpTargetAsmOperand;

2
lib/Target/Mips/MipsSEISelLowering.cpp
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@ -2947,6 +2947,8 @@ emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
// Insert the real bposge32 instruction to $BB.
BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
// Insert the real bposge32c instruction to $BB.
BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
// Fill $FBB.
unsigned VR2 = RegInfo.createVirtualRegister(RC);

2
test/MC/Disassembler/Mips/micromips-dsp/valid.txt
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@ -101,3 +101,5 @@
0x00 0x01 0x82 0x7c # CHECK: mthlip $1, $ac2
0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
0x00 0xc5 0x22 0x95 # CHECK: modsub $4, $5, $6
0x00 0x43 0x3c 0xbc # CHECK: mulsaq_s.w.ph $ac0, $3, $2

2
test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
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@ -123,3 +123,5 @@
0x00 0x22 0x1a 0x55 # CHECK: prepend $1, $2, 3
0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
0x00 0x64 0x2a 0x15 # CHECK: append $3, $4, 5
0x00 0x43 0x2c 0xbc # CHECK: mulsa.w.ph $ac0, $3, $2

3
test/MC/Disassembler/Mips/micromips-dspr3/valid.txt Normal file
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@ -0,0 +1,3 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dspr3 | FileCheck %s
0x43 0x20 0x00 0xab # CHECK: bposge32c 342

2
test/MC/Mips/micromips-dsp/valid.s
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@ -103,3 +103,5 @@
wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c]
wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
modsub $4, $5, $6 # CHECK: modsub $4, $5, $6 # encoding: [0x00,0xc5,0x22,0x95]
mulsaq_s.w.ph $ac0, $3, $2 # CHECK: mulsaq_s.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x3c,0xbc]

6
test/MC/Mips/micromips-dspr2/invalid.s
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@ -7,3 +7,9 @@
shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
shrl.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shrl.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
append $3, $4, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
append $3, $4, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
mulsa.w.ph $8, $3, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
mulsa.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
mulsaq_s.w.ph $8, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
mulsaq_s.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction

2
test/MC/Mips/micromips-dspr2/valid.s
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@ -125,3 +125,5 @@
wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c]
wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
append $3, $4, 5 # CHECK: append $3, $4, 5 # encoding: [0x00,0x64,0x2a,0x15]
mulsa.w.ph $ac0, $3, $2 # CHECK: mulsa.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x2c,0xbc]

4
test/MC/Mips/micromips-dspr3/valid.s Normal file
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@ -0,0 +1,4 @@
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr3 | FileCheck %s
.set noat
bposge32c 342 # CHECK: bposge32c 342 # encoding: [0x43,0x20,0x00,0xab]