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Fix Sparc 32bit Lowering to rebundle up v2i32 values.

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Summary: Fix LowerCall to rebundle v2i32 values after lowering and add testcase

Reviewers: jyknight

Subscribers: llvm-commits, jyknight

Differential Revision: http://reviews.llvm.org/D17615

llvm-svn: 262048
This commit is contained in:
Nirav Dave 2016-02-26 18:55:22 +00:00
parent 9bf70679ba
commit 9dd7b9a38b
2 changed files with 56 additions and 4 deletions
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27
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -999,10 +999,29 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
RVLocs[i].getValVT(), InFlag).getValue(1);
InFlag = Chain.getValue(2);
InVals.push_back(Chain.getValue(0));
if (RVLocs[i].getLocVT() == MVT::v2i32) {
SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
SDValue Lo = DAG.getCopyFromReg(
Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag);
Chain = Lo.getValue(1);
InFlag = Lo.getValue(2);
Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
DAG.getConstant(0, dl, MVT::i32));
SDValue Hi = DAG.getCopyFromReg(
Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag);
Chain = Hi.getValue(1);
InFlag = Hi.getValue(2);
Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
DAG.getConstant(1, dl, MVT::i32));
InVals.push_back(Vec);
} else {
Chain =
DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
RVLocs[i].getValVT(), InFlag)
.getValue(1);
InFlag = Chain.getValue(2);
InVals.push_back(Chain.getValue(0));
}
}
return Chain;

33
test/CodeGen/SPARC/vector-call.ll Normal file
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@ -0,0 +1,33 @@
; RUN: llc < %s -march=sparc | FileCheck %s
; Verify that we correctly handle vector types that appear directly
; during call lowering. These may cause issue as v2i32 is a legal type
; for the implementation of LDD
; CHECK-LABEL: fun16v:
; CHECK: foo1_16v
; CHECK: foo2_16v
define <2 x i16> @fun16v() #0 {
%1 = tail call <2 x i16> @foo1_16v()
%2 = tail call <2 x i16> @foo2_16v()
%3 = and <2 x i16> %2, %1
ret <2 x i16> %3
}
declare <2 x i16> @foo1_16v() #0
declare <2 x i16> @foo2_16v() #0
; CHECK-LABEL: fun32v:
; CHECK: foo1_32v
; CHECK: foo2_32v
define <2 x i32> @fun32v() #0 {
%1 = tail call <2 x i32> @foo1_32v()
%2 = tail call <2 x i32> @foo2_32v()
%3 = and <2 x i32> %2, %1
ret <2 x i32> %3
}
declare <2 x i32> @foo1_32v() #0
declare <2 x i32> @foo2_32v() #0