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Extend hasStoreToStackSlot with list of FI accesses.
For instructions that spill/fill to and from multiple frame-indices in a single instruction, hasStoreToStackSlot and hasLoadFromStackSlot should return an array of accesses, rather than just the first encounter of such an access. This better describes FI accesses for AArch64 (paired) LDP/STP instructions. Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar, MatzeB Reviewed By: MatzeB Differential Revision: https://reviews.llvm.org/D51537 llvm-svn: 341301
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@ -79,6 +79,13 @@ public:
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return Opc <= TargetOpcode::GENERIC_OP_END;
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}
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// Simple struct describing access to a FrameIndex.
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struct FrameAccess {
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const MachineMemOperand *MMO;
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int FI;
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FrameAccess(const MachineMemOperand *MMO, int FI) : MMO(MMO), FI(FI) {}
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};
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/// Given a machine instruction descriptor, returns the register
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/// class constraint for OpNum, or NULL.
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const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
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@ -246,14 +253,13 @@ public:
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}
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/// If the specified machine instruction has a load from a stack slot,
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/// return true along with the FrameIndex of the loaded stack slot and the
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/// machine mem operand containing the reference.
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/// return true along with the FrameIndices of the loaded stack slot and the
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/// machine mem operands containing the reference.
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/// If not, return false. Unlike isLoadFromStackSlot, this returns true for
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/// any instructions that loads from the stack. This is just a hint, as some
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/// cases may be missed.
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virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const;
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SmallVectorImpl<FrameAccess> &Accesses) const;
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/// If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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@ -284,14 +290,13 @@ public:
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}
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/// If the specified machine instruction has a store to a stack slot,
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/// return true along with the FrameIndex of the loaded stack slot and the
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/// machine mem operand containing the reference.
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/// return true along with the FrameIndices of the loaded stack slot and the
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/// machine mem operands containing the reference.
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/// If not, return false. Unlike isStoreToStackSlot,
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/// this returns true for any instructions that stores to the
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/// stack. This is just a hint, as some cases may be missed.
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virtual bool hasStoreToStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const;
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SmallVectorImpl<FrameAccess> &Accesses) const;
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/// Return true if the specified machine instruction
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/// is a copy of one stack slot to another and has no other effect.
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@ -750,18 +750,28 @@ static bool emitComments(const MachineInstr &MI, raw_ostream &CommentOS,
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const MachineFrameInfo &MFI = MF->getFrameInfo();
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bool Commented = false;
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auto getSize = [&MFI](
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const SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) {
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unsigned Size = 0;
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for (auto &A : Accesses)
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if (MFI.isSpillSlotObjectIndex(A.FI))
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Size += A.MMO->getSize();
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return Size;
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};
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// We assume a single instruction only has a spill or reload, not
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// both.
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const MachineMemOperand *MMO;
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SmallVector<TargetInstrInfo::FrameAccess, 2> Accesses;
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if (TII->isLoadFromStackSlotPostFE(MI, FI)) {
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if (MFI.isSpillSlotObjectIndex(FI)) {
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MMO = *MI.memoperands_begin();
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CommentOS << MMO->getSize() << "-byte Reload";
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Commented = true;
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}
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} else if (TII->hasLoadFromStackSlot(MI, MMO, FI)) {
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if (MFI.isSpillSlotObjectIndex(FI)) {
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CommentOS << MMO->getSize() << "-byte Folded Reload";
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} else if (TII->hasLoadFromStackSlot(MI, Accesses)) {
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if (auto Size = getSize(Accesses)) {
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CommentOS << Size << "-byte Folded Reload";
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Commented = true;
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}
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} else if (TII->isStoreToStackSlotPostFE(MI, FI)) {
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@ -770,9 +780,9 @@ static bool emitComments(const MachineInstr &MI, raw_ostream &CommentOS,
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CommentOS << MMO->getSize() << "-byte Spill";
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Commented = true;
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}
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} else if (TII->hasStoreToStackSlot(MI, MMO, FI)) {
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if (MFI.isSpillSlotObjectIndex(FI)) {
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CommentOS << MMO->getSize() << "-byte Folded Spill";
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} else if (TII->hasStoreToStackSlot(MI, Accesses)) {
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if (auto Size = getSize(Accesses)) {
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CommentOS << Size << "-byte Folded Spill";
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Commented = true;
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}
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}
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@ -470,7 +470,7 @@ bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
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MachineFunction *MF, unsigned &Reg) {
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const MachineFrameInfo &FrameInfo = MF->getFrameInfo();
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int FI;
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const MachineMemOperand *MMO;
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SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
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// TODO: Handle multiple stores folded into one.
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if (!MI.hasOneMemOperand())
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@ -478,7 +478,7 @@ bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
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// To identify a spill instruction, use the same criteria as in AsmPrinter.
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if (!((TII->isStoreToStackSlotPostFE(MI, FI) ||
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TII->hasStoreToStackSlot(MI, MMO, FI)) &&
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TII->hasStoreToStackSlot(MI, Accesses)) &&
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FrameInfo.isSpillSlotObjectIndex(FI)))
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return false;
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@ -3120,18 +3120,24 @@ void RAGreedy::reportNumberOfSplillsReloads(MachineLoop *L, unsigned &Reloads,
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// Handle blocks that were not included in subloops.
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if (Loops->getLoopFor(MBB) == L)
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for (MachineInstr &MI : *MBB) {
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const MachineMemOperand *MMO;
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SmallVector<TargetInstrInfo::FrameAccess, 2> Accesses;
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if (TII->isLoadFromStackSlot(MI, FI) && MFI.isSpillSlotObjectIndex(FI))
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++Reloads;
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else if (TII->hasLoadFromStackSlot(MI, MMO, FI) &&
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MFI.isSpillSlotObjectIndex(FI))
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else if (TII->hasLoadFromStackSlot(MI, Accesses) &&
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llvm::any_of(Accesses,
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[&MFI](const TargetInstrInfo::FrameAccess &A) {
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return MFI.isSpillSlotObjectIndex(A.FI);
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}))
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++FoldedReloads;
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else if (TII->isStoreToStackSlot(MI, FI) &&
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MFI.isSpillSlotObjectIndex(FI))
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++Spills;
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else if (TII->hasStoreToStackSlot(MI, MMO, FI) &&
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MFI.isSpillSlotObjectIndex(FI))
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else if (TII->hasStoreToStackSlot(MI, Accesses) &&
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llvm::any_of(Accesses,
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[&MFI](const TargetInstrInfo::FrameAccess &A) {
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return MFI.isSpillSlotObjectIndex(A.FI);
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}))
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++FoldedSpills;
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}
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@ -339,42 +339,37 @@ bool TargetInstrInfo::PredicateInstruction(
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return MadeChange;
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}
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bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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bool TargetInstrInfo::hasLoadFromStackSlot(
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const MachineInstr &MI, SmallVectorImpl<FrameAccess> &Accesses) const {
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size_t StartSize = Accesses.size();
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for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
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oe = MI.memoperands_end();
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o != oe; ++o) {
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if ((*o)->isLoad()) {
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if (const FixedStackPseudoSourceValue *Value =
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dyn_cast_or_null<FixedStackPseudoSourceValue>(
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(*o)->getPseudoValue())) {
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FrameIndex = Value->getFrameIndex();
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MMO = *o;
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return true;
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}
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(*o)->getPseudoValue()))
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Accesses.emplace_back(*o, Value->getFrameIndex());
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}
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}
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return false;
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return Accesses.size() != StartSize;
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}
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bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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bool TargetInstrInfo::hasStoreToStackSlot(
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const MachineInstr &MI, SmallVectorImpl<FrameAccess> &Accesses) const {
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size_t StartSize = Accesses.size();
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for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
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oe = MI.memoperands_end();
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o != oe; ++o) {
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if ((*o)->isStore()) {
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if (const FixedStackPseudoSourceValue *Value =
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dyn_cast_or_null<FixedStackPseudoSourceValue>(
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(*o)->getPseudoValue())) {
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FrameIndex = Value->getFrameIndex();
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MMO = *o;
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return true;
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}
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(*o)->getPseudoValue()))
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Accesses.emplace_back(*o, Value->getFrameIndex());
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}
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}
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return false;
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return Accesses.size() != StartSize;
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}
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bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
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@ -1172,8 +1172,12 @@ unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const {
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const MachineMemOperand *Dummy;
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return MI.mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
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SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
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if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses)) {
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FrameIndex = Accesses.begin()->FI;
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return true;
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}
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return false;
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}
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void ARMBaseInstrInfo::
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@ -1386,8 +1390,12 @@ unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const {
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const MachineMemOperand *Dummy;
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return MI.mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
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SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
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if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses)) {
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FrameIndex = Accesses.begin()->FI;
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return true;
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}
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return false;
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}
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/// Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
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@ -335,37 +335,37 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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/// This function checks if the instruction or bundle of instructions
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/// has load from stack slot and returns frameindex and machine memory
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/// operand of that instruction if true.
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bool HexagonInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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bool HexagonInstrInfo::hasLoadFromStackSlot(
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const MachineInstr &MI,
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SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const {
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if (MI.isBundle()) {
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const MachineBasicBlock *MBB = MI.getParent();
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MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
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for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
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if (TargetInstrInfo::hasLoadFromStackSlot(*MII, MMO, FrameIndex))
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if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
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return true;
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return false;
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}
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return TargetInstrInfo::hasLoadFromStackSlot(MI, MMO, FrameIndex);
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return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
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}
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/// This function checks if the instruction or bundle of instructions
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/// has store to stack slot and returns frameindex and machine memory
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/// operand of that instruction if true.
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bool HexagonInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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bool HexagonInstrInfo::hasStoreToStackSlot(
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const MachineInstr &MI,
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SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const {
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if (MI.isBundle()) {
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const MachineBasicBlock *MBB = MI.getParent();
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MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
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for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
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if (TargetInstrInfo::hasStoreToStackSlot(*MII, MMO, FrameIndex))
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if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
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return true;
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return false;
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}
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return TargetInstrInfo::hasStoreToStackSlot(MI, MMO, FrameIndex);
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return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
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}
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/// This function can analyze one/two way branching only and should (mostly) be
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@ -69,16 +69,16 @@ public:
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/// Check if the instruction or the bundle of instructions has
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/// load from stack slots. Return the frameindex and machine memory operand
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/// if true.
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bool hasLoadFromStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const override;
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bool hasLoadFromStackSlot(
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const MachineInstr &MI,
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SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const override;
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/// Check if the instruction or the bundle of instructions has
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/// store to stack slots. Return the frameindex and machine memory operand
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/// if true.
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bool hasStoreToStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const override;
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bool hasStoreToStackSlot(
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const MachineInstr &MI,
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SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const override;
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/// Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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@ -733,8 +733,11 @@ unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
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if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
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return Reg;
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// Check for post-frame index elimination operations
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const MachineMemOperand *Dummy;
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return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
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SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
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if (hasLoadFromStackSlot(MI, Accesses)){
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FrameIndex = Accesses.begin()->FI;
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return 1;
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}
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}
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return 0;
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}
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@ -411,8 +411,11 @@ unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
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if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
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return Reg;
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// Check for post-frame index elimination operations
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const MachineMemOperand *Dummy;
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return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
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SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
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if (hasLoadFromStackSlot(MI, Accesses)) {
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FrameIndex = Accesses.begin()->FI;
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return 1;
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}
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}
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return 0;
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}
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@ -441,8 +444,11 @@ unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
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if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
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return Reg;
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// Check for post-frame index elimination operations
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const MachineMemOperand *Dummy;
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return hasStoreToStackSlot(MI, Dummy, FrameIndex);
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SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
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if (hasStoreToStackSlot(MI, Accesses)) {
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FrameIndex = Accesses.begin()->FI;
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return 1;
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}
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}
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return 0;
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}
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@ -206,11 +206,11 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
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; CHECK-NEXT: eor w8, w0, w1
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; CHECK-NEXT: and w20, w8, #0xffff00
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; CHECK-NEXT: mov w0, w20
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; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: mov w19, w1
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; CHECK-NEXT: bl use32
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; CHECK-NEXT: eor w0, w20, w19
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; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%n0 = xor i32 %x, %y
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@ -225,12 +225,12 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x20, [sp, #-32]! // 8-byte Folded Spill
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; CHECK-NEXT: eor w0, w0, w1
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; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: mov w19, w1
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; CHECK-NEXT: and w20, w0, #0xffff00
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; CHECK-NEXT: bl use32
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; CHECK-NEXT: eor w0, w20, w19
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; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%n0 = xor i32 %x, %y
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@ -212,11 +212,11 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
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; CHECK-NEXT: eor w8, w0, w1
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; CHECK-NEXT: and w20, w8, #0x55555555
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; CHECK-NEXT: mov w0, w20
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; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: mov w19, w1
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; CHECK-NEXT: bl use32
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; CHECK-NEXT: eor w0, w20, w19
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; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%n0 = xor i32 %x, %y
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@ -231,12 +231,12 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x20, [sp, #-32]! // 8-byte Folded Spill
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; CHECK-NEXT: eor w0, w0, w1
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; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: mov w19, w1
|
||||
; CHECK-NEXT: and w20, w0, #0x55555555
|
||||
; CHECK-NEXT: bl use32
|
||||
; CHECK-NEXT: eor w0, w20, w19
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor i32 %x, %y
|
||||
|
@ -208,11 +208,11 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
|
||||
; CHECK-NEXT: eor w8, w0, w1
|
||||
; CHECK-NEXT: and w20, w8, #0xf0f0f0f
|
||||
; CHECK-NEXT: mov w0, w20
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: mov w19, w1
|
||||
; CHECK-NEXT: bl use32
|
||||
; CHECK-NEXT: eor w0, w20, w19
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor i32 %x, %y
|
||||
@ -227,12 +227,12 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x20, [sp, #-32]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: eor w0, w0, w1
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: mov w19, w1
|
||||
; CHECK-NEXT: and w20, w0, #0xf0f0f0f
|
||||
; CHECK-NEXT: bl use32
|
||||
; CHECK-NEXT: eor w0, w20, w19
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor i32 %x, %y
|
||||
|
@ -201,11 +201,11 @@ define i32 @in_multiuse_A_constmask(i32 %x, i32 %y, i32 %z) nounwind {
|
||||
; CHECK-NEXT: eor w8, w0, w1
|
||||
; CHECK-NEXT: and w20, w8, #0xffff
|
||||
; CHECK-NEXT: mov w0, w20
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: mov w19, w1
|
||||
; CHECK-NEXT: bl use32
|
||||
; CHECK-NEXT: eor w0, w20, w19
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor i32 %x, %y
|
||||
@ -220,12 +220,12 @@ define i32 @in_multiuse_B_constmask(i32 %x, i32 %y, i32 %z) nounwind {
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x20, [sp, #-32]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: eor w0, w0, w1
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: mov w19, w1
|
||||
; CHECK-NEXT: and w20, w0, #0xffff
|
||||
; CHECK-NEXT: bl use32
|
||||
; CHECK-NEXT: eor w0, w20, w19
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor i32 %x, %y
|
||||
|
@ -558,11 +558,11 @@ define i32 @in_multiuse_A(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind {
|
||||
; CHECK-NEXT: eor w8, w0, w1
|
||||
; CHECK-NEXT: and w20, w8, w3
|
||||
; CHECK-NEXT: mov w0, w20
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: mov w19, w1
|
||||
; CHECK-NEXT: bl use32
|
||||
; CHECK-NEXT: eor w0, w20, w19
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor i32 %x, %y
|
||||
@ -576,12 +576,12 @@ define i32 @in_multiuse_B(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind {
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x20, [sp, #-32]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: eor w0, w0, w1
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp x19, x30, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: mov w19, w1
|
||||
; CHECK-NEXT: and w20, w0, w3
|
||||
; CHECK-NEXT: bl use32
|
||||
; CHECK-NEXT: eor w0, w20, w19
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x19, x30, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldr x20, [sp], #32 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor i32 %x, %y
|
||||
|
@ -141,8 +141,8 @@ define <5 x float> @sin_v5f32(<5 x float> %x) nounwind {
|
||||
; CHECK-LABEL: sin_v5f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str d12, [sp, #-48]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp d11, d10, [sp, #8] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp d9, d8, [sp, #24] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp d11, d10, [sp, #8] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: mov v8.16b, v4.16b
|
||||
; CHECK-NEXT: mov v9.16b, v3.16b
|
||||
@ -165,8 +165,8 @@ define <5 x float> @sin_v5f32(<5 x float> %x) nounwind {
|
||||
; CHECK-NEXT: mov v2.16b, v10.16b
|
||||
; CHECK-NEXT: mov v3.16b, v9.16b
|
||||
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d11, d10, [sp, #8] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d11, d10, [sp, #8] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: mov v4.16b, v0.16b
|
||||
; CHECK-NEXT: mov v0.16b, v12.16b
|
||||
; CHECK-NEXT: ldr d12, [sp], #48 // 8-byte Folded Reload
|
||||
@ -178,9 +178,9 @@ define <5 x float> @sin_v5f32(<5 x float> %x) nounwind {
|
||||
define <6 x float> @sin_v6f32(<6 x float> %x) nounwind {
|
||||
; CHECK-LABEL: sin_v6f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: stp d13, d12, [sp, #-64]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp d11, d10, [sp, #16] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp d9, d8, [sp, #32] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp d13, d12, [sp, #-64]! // 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d11, d10, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: mov v8.16b, v5.16b
|
||||
; CHECK-NEXT: mov v9.16b, v4.16b
|
||||
@ -207,12 +207,12 @@ define <6 x float> @sin_v6f32(<6 x float> %x) nounwind {
|
||||
; CHECK-NEXT: mov v3.16b, v10.16b
|
||||
; CHECK-NEXT: mov v4.16b, v9.16b
|
||||
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d9, d8, [sp, #32] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d11, d10, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d11, d10, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: mov v5.16b, v0.16b
|
||||
; CHECK-NEXT: mov v0.16b, v13.16b
|
||||
; CHECK-NEXT: mov v1.16b, v12.16b
|
||||
; CHECK-NEXT: ldp d13, d12, [sp], #64 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d13, d12, [sp], #64 // 16-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%r = call <6 x float> @llvm.sin.v6f32(<6 x float> %x)
|
||||
ret <6 x float> %r
|
||||
@ -222,7 +222,7 @@ define <3 x double> @sin_v3f64(<3 x double> %x) nounwind {
|
||||
; CHECK-LABEL: sin_v3f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str d10, [sp, #-32]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp d9, d8, [sp, #8] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: stp d9, d8, [sp, #8] // 16-byte Folded Spill
|
||||
; CHECK-NEXT: str x30, [sp, #24] // 8-byte Folded Spill
|
||||
; CHECK-NEXT: mov v8.16b, v2.16b
|
||||
; CHECK-NEXT: mov v9.16b, v1.16b
|
||||
@ -235,7 +235,7 @@ define <3 x double> @sin_v3f64(<3 x double> %x) nounwind {
|
||||
; CHECK-NEXT: bl sin
|
||||
; CHECK-NEXT: mov v1.16b, v9.16b
|
||||
; CHECK-NEXT: ldr x30, [sp, #24] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d9, d8, [sp, #8] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d9, d8, [sp, #8] // 16-byte Folded Reload
|
||||
; CHECK-NEXT: mov v2.16b, v0.16b
|
||||
; CHECK-NEXT: mov v0.16b, v10.16b
|
||||
; CHECK-NEXT: ldr d10, [sp], #32 // 8-byte Folded Reload
|
||||
|
Loading…
Reference in New Issue
Block a user