RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-01 00:25:01 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix single precision FP constants on SPU. They are actually legal,

Browse Source 
which allows us to kill a target-specific node.

llvm-svn: 47127
This commit is contained in:
Nate Begeman 2008-02-14 18:43:04 +00:00
parent 27f4dab7a3
commit 9deedb0114
3 changed files with 9 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -158,7 +158,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
// SPU constant load actions are custom lowered:
setOperationAction(ISD::Constant, MVT::i64, Custom);
setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
// SPU's loads and stores have to be custom lowered:
@ -420,7 +420,6 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
"SPUISD::ROTBYTES_LEFT_CHAINED";
node_names[(unsigned) SPUISD::FSMBI] = "SPUISD::FSMBI";
node_names[(unsigned) SPUISD::SELB] = "SPUISD::SELB";
node_names[(unsigned) SPUISD::SFPConstant] = "SPUISD::SFPConstant";
node_names[(unsigned) SPUISD::FPInterp] = "SPUISD::FPInterp";
node_names[(unsigned) SPUISD::FPRecipEst] = "SPUISD::FPRecipEst";
node_names[(unsigned) SPUISD::SEXT32TO64] = "SPUISD::SEXT32TO64";
@ -851,12 +850,7 @@ LowerConstant(SDOperand Op, SelectionDAG &DAG) {
return SDOperand();
}
//! Custom lower single precision floating point constants
/*!
"float" immediates can be lowered as if they were unsigned 32-bit integers.
The SPUISD::SFPConstant pseudo-instruction handles this in the instruction
target description.
*/
//! Custom lower double precision floating point constants
static SDOperand
LowerConstantFP(SDOperand Op, SelectionDAG &DAG) {
unsigned VT = Op.getValueType();
@ -865,11 +859,7 @@ LowerConstantFP(SDOperand Op, SelectionDAG &DAG) {
assert((FP != 0) &&
"LowerConstantFP: Node is not ConstantFPSDNode");
if (VT == MVT::f32) {
float targetConst = FP->getValueAPF().convertToFloat();
return DAG.getNode(SPUISD::SFPConstant, VT,
DAG.getTargetConstantFP(targetConst, VT));
} else if (VT == MVT::f64) {
if (VT == MVT::f64) {
uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
return DAG.getNode(ISD::BIT_CONVERT, VT,
LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG));

1
lib/Target/CellSPU/SPUISelLowering.h
View File

@ -61,7 +61,6 @@ namespace llvm {
ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain
FSMBI, ///< Form Select Mask for Bytes, Immediate
SELB, ///< Select bits -> (b & mask) | (a & ~mask)
SFPConstant, ///< Single precision floating point constant
FPInterp, ///< Floating point interpolate
FPRecipEst, ///< Floating point reciprocal estimate
SEXT32TO64, ///< Sign-extended 32-bit const -> 64-bits

12
lib/Target/CellSPU/SPUInstrInfo.td
View File

@ -349,12 +349,12 @@ def ILr32:
def ILf32:
RI16Form<0b100000010, (outs R32FP:$rT), (ins s16imm_f32:$val),
"il\t$rT, $val", ImmLoad,
[(set R32FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>;
[(set R32FP:$rT, fpimmSExt16:$val)]>;
def ILf64:
RI16Form<0b100000010, (outs R64FP:$rT), (ins s16imm_f64:$val),
"il\t$rT, $val", ImmLoad,
[(set R64FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>;
[(set R64FP:$rT, fpimmSExt16:$val)]>;
def ILHUv4i32:
RI16Form<0b010000010, (outs VECREG:$rT), (ins u16imm:$val),
@ -370,7 +370,7 @@ def ILHUr32:
def ILHUf32:
RI16Form<0b010000010, (outs R32FP:$rT), (ins f16imm:$val),
"ilhu\t$rT, $val", ImmLoad,
[(set R32FP:$rT, (SPUFPconstant hi16_f32:$val))]>;
[(set R32FP:$rT, hi16_f32:$val)]>;
// ILHUhi: Used for loading high portion of an address. Note the symbolHi
// printer used for the operand.
@ -405,12 +405,12 @@ def ILAr32:
def ILAf32:
RI18Form<0b1000010, (outs R32FP:$rT), (ins f18imm:$val),
"ila\t$rT, $val", LoadNOP,
[(set R32FP:$rT, (SPUFPconstant fpimm18:$val))]>;
[(set R32FP:$rT, fpimm18:$val)]>;
def ILAf64:
RI18Form<0b1000010, (outs R64FP:$rT), (ins f18imm_f64:$val),
"ila\t$rT, $val", LoadNOP,
[(set R64FP:$rT, (SPUFPconstant fpimm18:$val))]>;
[(set R64FP:$rT, fpimm18:$val)]>;
def ILAlo:
RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLo:$val),
@ -3236,7 +3236,7 @@ def : Pat<(i32 imm:$imm),
(IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
// Single precision float constants:
def : Pat<(SPUFPconstant (f32 fpimm:$imm)),
def : Pat<(f32 fpimm:$imm),
(IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
// General constant 32-bit vectors