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Rename SelectionDAGISel's FastISel to Fast, to begin to make
room for the new FastISel instruction selection code. llvm-svn: 54749
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@ -42,12 +42,12 @@ public:
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MachineBasicBlock *BB;
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AliasAnalysis *AA;
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CollectorMetadata *GCI;
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bool FastISel;
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bool Fast;
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std::vector<SDNode*> TopOrder;
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static char ID;
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explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) :
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FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), FastISel(fast), DAGSize(0) {}
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FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), Fast(fast), DAGSize(0) {}
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TargetLowering &getTargetLowering() { return TLI; }
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@ -5379,7 +5379,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
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if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
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if (!FastISel && EnableValueProp)
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if (!Fast && EnableValueProp)
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ComputeLiveOutVRegInfo(DAG);
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// Third, instruction select all of the operations to machine code, adding the
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@ -5448,7 +5448,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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BasicBlock *LLVMBB = &*I;
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PHINodesToUpdate.clear();
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if (!FastISel || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB]))
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if (!Fast || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB]))
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SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
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FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
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}
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@ -5696,7 +5696,7 @@ ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
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RegisterScheduler::setDefault(Ctor);
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}
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ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
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ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, Fast);
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Scheduler->Run();
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return Scheduler;
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