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[AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
- Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target. - Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS. Differential Revision: https://reviews.llvm.org/D43736 llvm-svn: 328349
This commit is contained in:
Tony Tye
parent
3df7615245
commit
a07033cf3c
@ -64,9 +64,7 @@ specify the target triple:
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============ ==============================================================
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Environment Description
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============ ==============================================================
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*<empty>* Defaults to ``opencl``.
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``opencl`` OpenCL compute kernel (see :ref:`amdgpu-opencl`).
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``hcc`` AMD HC language compute kernel (see :ref:`amdgpu-hcc`).
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*<empty>* Default.
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============ ==============================================================
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.. _amdgpu-processors:
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@ -3787,35 +3785,37 @@ Source Languages
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OpenCL
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------
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When generating code for the OpenCL language the target triple environment
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should be ``opencl`` or ``amdgizcl`` (see :ref:`amdgpu-target-triples`).
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When the language is OpenCL the following differences occur:
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1. The OpenCL memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
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2. The AMDGPU backend adds additional arguments to the kernel.
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2. The AMDGPU backend appends additional arguments to the kernel's explicit
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arguments for the AMDHSA OS (see
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:ref:`opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table`).
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3. Additional metadata is generated
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(:ref:`amdgpu-amdhsa-hsa-code-object-metadata`).
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(see :ref:`amdgpu-amdhsa-hsa-code-object-metadata`).
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.. TODO
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Specify what affect this has. Hidden arguments added. Additional metadata
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generated.
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.. table:: OpenCL kernel implicit arguments appended for AMDHSA OS
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:name: opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table
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======== ==== ========= ===========================================
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Position Byte Byte Description
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Size Alignment
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======== ==== ========= ===========================================
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0 8 8 OpenCL Global Offset X
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1 8 8 OpenCL Global Offset Y
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2 8 8 OpenCL Global Offset Z
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3 8 8 OpenCL printf buffer
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======== ==== ========= ===========================================
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.. _amdgpu-hcc:
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HCC
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---
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When generating code for the OpenCL language the target triple environment
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should be ``hcc`` (see :ref:`amdgpu-target-triples`).
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When the language is OpenCL the following differences occur:
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When the language is HCC the following differences occur:
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1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
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.. TODO
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Specify what affect this has.
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Assembler
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---------
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@ -203,7 +203,6 @@ public:
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Itanium,
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Cygnus,
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CoreCLR,
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OpenCL,
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Simulator, // Simulator variants of other systems, e.g., Apple's iOS
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LastEnvironmentType = Simulator
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};
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@ -233,7 +233,6 @@ StringRef Triple::getEnvironmentTypeName(EnvironmentType Kind) {
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case Itanium: return "itanium";
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case Cygnus: return "cygnus";
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case CoreCLR: return "coreclr";
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case OpenCL: return "opencl";
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case Simulator: return "simulator";
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}
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@ -523,7 +522,6 @@ static Triple::EnvironmentType parseEnvironment(StringRef EnvironmentName) {
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.StartsWith("itanium", Triple::Itanium)
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.StartsWith("cygnus", Triple::Cygnus)
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.StartsWith("coreclr", Triple::CoreCLR)
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.StartsWith("opencl", Triple::OpenCL)
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.StartsWith("simulator", Triple::Simulator)
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.Default(Triple::UnknownEnvironment);
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}
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@ -212,11 +212,6 @@ public:
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return TargetTriple.getOS() == Triple::Mesa3D;
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}
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bool isOpenCLEnv() const {
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return TargetTriple.getEnvironment() == Triple::OpenCL ||
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TargetTriple.getEnvironmentName() == "amdgizcl";
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}
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bool isAmdPalOS() const {
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return TargetTriple.getOS() == Triple::AMDPAL;
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}
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@ -543,12 +538,13 @@ public:
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return isAmdHsaOS() ? 8 : 4;
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}
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/// \returns Number of bytes of arguments that are passed to a shader or
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/// kernel in addition to the explicit ones declared for the function.
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unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
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if (isMesaKernel(MF))
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return 16;
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if (isAmdHsaOS() && isOpenCLEnv())
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return 32;
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return 0;
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return AMDGPU::getIntegerAttribute(
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MF.getFunction(), "amdgpu-implicitarg-num-bytes", 0);
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}
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// Scratch is allocated in 256 dword per wave blocks for the entire
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@ -1,12 +1,10 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA-NOENV: kernarg_segment_byte_size = 0
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; HSA-OPENCL: kernarg_segment_byte_size = 32
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; HSA: kernarg_segment_byte_size = 0
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; MESA: kernarg_segment_byte_size = 16
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; HSA: s_load_dword s0, s[4:5], 0x0
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@ -17,11 +15,24 @@ define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 32
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; MESA: kernarg_segment_byte_size = 16
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; HSA: s_load_dword s0, s[4:5], 0x0
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define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA-NOENV: kernarg_segment_byte_size = 112
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; HSA-OPENCL: kernarg_segment_byte_size = 144
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; HSA: kernarg_segment_byte_size = 112
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; MESA: kernarg_segment_byte_size = 464
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; HSA: s_load_dword s0, s[4:5], 0x1c
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@ -32,6 +43,20 @@ define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 144
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; MESA: kernarg_segment_byte_size = 464
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; HSA: s_load_dword s0, s[4:5], 0x1c
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define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}func_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: s_mov_b64 s[8:9], s[6:7]
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@ -43,7 +68,25 @@ define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
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; HSA: flat_load_dword v0, v[0:1]
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @func_implicitarg_ptr() #1 {
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define void @func_implicitarg_ptr() #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: s_mov_b64 s[8:9], s[6:7]
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; MESA: s_mov_b32 s11, 0xf000
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; MESA: s_mov_b32 s10, -1
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; MESA: buffer_load_dword v0, off, s[8:11], 0
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; HSA: v_mov_b32_e32 v0, s6
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; HSA: v_mov_b32_e32 v1, s7
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; HSA: flat_load_dword v0, v[0:1]
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @opencl_func_implicitarg_ptr() #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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@ -52,8 +95,7 @@ define void @func_implicitarg_ptr() #1 {
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA-NOENV: kernarg_segment_byte_size = 0
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; HSA-OPENCL: kernarg_segment_byte_size = 32
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; HSA: kernarg_segment_byte_size = 0
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; MESA: kernarg_segment_byte_size = 16
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; GCN: s_mov_b64 s[6:7], s[4:5]
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; GCN: s_swappc_b64
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@ -62,10 +104,20 @@ define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 32
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; MESA: kernarg_segment_byte_size = 16
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; GCN: s_mov_b64 s[6:7], s[4:5]
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; GCN: s_swappc_b64
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define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA-OPENCL: kernarg_segment_byte_size = 144
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; HSA-NOENV: kernarg_segment_byte_size = 112
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; HSA: kernarg_segment_byte_size = 112
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; MESA: kernarg_segment_byte_size = 464
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; HSA: s_add_u32 s6, s4, 0x70
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@ -78,11 +130,35 @@ define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 {
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 144
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; MESA: kernarg_segment_byte_size = 464
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; HSA: s_add_u32 s6, s4, 0x70
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; MESA: s_add_u32 s6, s4, 0x1c0
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; GCN: s_addc_u32 s7, s5, 0{{$}}
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; GCN: s_swappc_b64
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define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func([112 x i8]) #1 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func:
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; GCN-NOT: s6
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; GCN-NOT: s7
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; GCN-NOT: s[6:7]
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define void @func_call_implicitarg_ptr_func() #1 {
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define void @func_call_implicitarg_ptr_func() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_call_implicitarg_ptr_func:
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; GCN-NOT: s6
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; GCN-NOT: s7
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; GCN-NOT: s[6:7]
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define void @opencl_func_call_implicitarg_ptr_func() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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@ -104,7 +180,34 @@ define void @func_call_implicitarg_ptr_func() #1 {
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; HSA: flat_load_dword v0, v[0:1]
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; GCN: s_waitcnt vmcnt(0)
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define void @func_kernarg_implicitarg_ptr() #1 {
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define void @func_kernarg_implicitarg_ptr() #0 {
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%kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
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%cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
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%load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: s_mov_b64 s[12:13], s[6:7]
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; MESA: s_mov_b32 s15, 0xf000
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; MESA: s_mov_b32 s14, -1
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; MESA: buffer_load_dword v0, off, s[12:15], 0
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; HSA: v_mov_b32_e32 v0, s6
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; HSA: v_mov_b32_e32 v1, s7
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; HSA: flat_load_dword v0, v[0:1]
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; MESA: s_mov_b32 s10, s14
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; MESA: s_mov_b32 s11, s15
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; MESA: buffer_load_dword v0, off, s[8:11], 0
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; HSA: v_mov_b32_e32 v0, s8
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; HSA: v_mov_b32_e32 v1, s9
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; HSA: flat_load_dword v0, v[0:1]
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; GCN: s_waitcnt vmcnt(0)
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define void @opencl_func_kernarg_implicitarg_ptr() #0 {
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%kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
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@ -129,5 +232,5 @@ declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2
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declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
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attributes #0 = { nounwind noinline }
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attributes #1 = { nounwind noinline }
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attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="32" }
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attributes #2 = { nounwind readnone speculatable }
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@ -1,9 +1,6 @@
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
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; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
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; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
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; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
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; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
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; ALL-LABEL: {{^}}test:
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; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
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@ -32,8 +29,7 @@ define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
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}
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; ALL-LABEL: {{^}}test_implicit_alignment
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; HSA-NOENV: kernarg_segment_byte_size = 10
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; HSA-OPENCL: kernarg_segment_byte_size = 48
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; HSA: kernarg_segment_byte_size = 10
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; OS-MESA3D: kernarg_segment_byte_size = 28
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; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
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; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
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@ -49,6 +45,23 @@ define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x
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ret void
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}
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; ALL-LABEL: {{^}}opencl_test_implicit_alignment
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; HSA: kernarg_segment_byte_size = 48
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; OS-MESA3D: kernarg_segment_byte_size = 28
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; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
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; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
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; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
|
||||
; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
|
||||
; MESA: buffer_store_dword [[V_VAL]]
|
||||
; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
|
||||
define amdgpu_kernel void @opencl_test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #2 {
|
||||
%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
|
||||
%arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
|
||||
%val = load i32, i32 addrspace(4)* %arg.ptr
|
||||
store i32 %val, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL-LABEL: {{^}}test_no_kernargs:
|
||||
; HSA: enable_sgpr_kernarg_segment_ptr = 1
|
||||
; HSA: s_load_dword s{{[0-9]+}}, s[4:5]
|
||||
@ -66,3 +79,4 @@ declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind }
|
||||
attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="32" }
|
||||
|
||||
@ -283,12 +283,6 @@ TEST(TripleTest, ParsedIDs) {
|
||||
EXPECT_EQ(Triple::AMDHSA, T.getOS());
|
||||
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
|
||||
|
||||
T = Triple("amdgcn-amd-amdhsa-opencl");
|
||||
EXPECT_EQ(Triple::amdgcn, T.getArch());
|
||||
EXPECT_EQ(Triple::AMD, T.getVendor());
|
||||
EXPECT_EQ(Triple::AMDHSA, T.getOS());
|
||||
EXPECT_EQ(Triple::OpenCL, T.getEnvironment());
|
||||
|
||||
T = Triple("amdgcn-amd-amdpal");
|
||||
EXPECT_EQ(Triple::amdgcn, T.getArch());
|
||||
EXPECT_EQ(Triple::AMD, T.getVendor());
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user