[llvm-exegesis] Fix invalid return type and add a Dump function.

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D53020

llvm-svn: 344050
This commit is contained in:
Guillaume Chatelet 2018-10-09 14:51:29 +00:00
parent 0b30701f8e
commit a0bccc42f3
2 changed files with 62 additions and 8 deletions

View File

@ -29,7 +29,10 @@ unsigned Variable::getPrimaryOperandIndex() const {
bool Variable::hasTiedOperands() const { return TiedOperands.size() > 1; }
bool Operand::getIndex() const { return Index; }
unsigned Operand::getIndex() const {
assert(Index >= 0 && "Index must be set");
return Index;
}
bool Operand::isExplicit() const { return Info; }
@ -57,13 +60,15 @@ bool Operand::isImmediate() const {
getExplicitOperandInfo().OperandType == llvm::MCOI::OPERAND_IMMEDIATE;
}
int Operand::getTiedToIndex() const {
assert(isTied());
unsigned Operand::getTiedToIndex() const {
assert(isTied() && "Operand must be tied to get the tied index");
assert(TiedToIndex >= 0 && "TiedToIndex must be set");
return TiedToIndex;
}
int Operand::getVariableIndex() const {
assert(isVariable());
unsigned Operand::getVariableIndex() const {
assert(isVariable() && "Operand must be variable to get the Variable index");
assert(VariableIndex >= 0 && "VariableIndex must be set");
return VariableIndex;
}
@ -179,6 +184,51 @@ bool Instruction::hasAliasingRegisters() const {
return AllDefRegs.anyCommon(AllUseRegs);
}
void Instruction::Dump(const llvm::MCRegisterInfo &RegInfo,
llvm::raw_ostream &Stream) const {
for (const auto &Op : Operands) {
Stream << "- Op" << Op.getIndex();
if (Op.isExplicit())
Stream << " Explicit";
if (Op.isImplicit())
Stream << " Implicit";
if (Op.isUse())
Stream << " Use";
if (Op.isDef())
Stream << " Def";
if (Op.isImmediate())
Stream << " Immediate";
if (Op.isMemory())
Stream << " Memory";
if (Op.isReg()) {
if (Op.isImplicitReg())
Stream << " Reg(" << RegInfo.getName(Op.getImplicitReg()) << ")";
else
Stream << " RegClass("
<< RegInfo.getRegClassName(
&RegInfo.getRegClass(Op.Info->RegClass))
<< ")";
}
if (Op.isTied())
Stream << " TiedToOp" << Op.getTiedToIndex();
Stream << "\n";
}
for (const auto &Var : Variables) {
Stream << "- Var" << Var.getIndex();
for (auto OperandIndex : Var.TiedOperands)
Stream << " Op" << OperandIndex;
Stream << "\n";
}
if (hasMemoryOperands())
Stream << "- hasMemoryOperands\n";
if (hasAliasingImplicitRegisters())
Stream << "- hasAliasingImplicitRegisters (execution is always serial)\n";
if (hasTiedRegisters())
Stream << "- hasTiedRegisters (execution is always serial)\n";
if (hasAliasingRegisters())
Stream << "- hasAliasingRegisters\n";
}
bool RegisterOperandAssignment::
operator==(const RegisterOperandAssignment &Other) const {
return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);

View File

@ -62,7 +62,6 @@ struct Variable {
// - VariableIndex: the index of the Variable holding the value for this Operand
// or -1 if this operand is implicit.
struct Operand {
bool getIndex() const;
bool isExplicit() const;
bool isImplicit() const;
bool isImplicitReg() const;
@ -73,8 +72,9 @@ struct Operand {
bool isVariable() const;
bool isMemory() const;
bool isImmediate() const;
int getTiedToIndex() const;
int getVariableIndex() const;
unsigned getIndex() const;
unsigned getTiedToIndex() const;
unsigned getVariableIndex() const;
unsigned getImplicitReg() const;
const RegisterAliasingTracker &getRegisterAliasing() const;
const llvm::MCOperandInfo &getExplicitOperandInfo() const;
@ -118,6 +118,10 @@ struct Instruction {
// aliasing Use and Def registers.
bool hasAliasingRegisters() const;
// Convenient function to help with debugging.
void Dump(const llvm::MCRegisterInfo &RegInfo,
llvm::raw_ostream &Stream) const;
const llvm::MCInstrDesc *Description; // Never nullptr.
llvm::SmallVector<Operand, 8> Operands;
llvm::SmallVector<Variable, 4> Variables;