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[llvm-exegesis] Fix invalid return type and add a Dump function.
Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D53020 llvm-svn: 344050
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@ -29,7 +29,10 @@ unsigned Variable::getPrimaryOperandIndex() const {
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bool Variable::hasTiedOperands() const { return TiedOperands.size() > 1; }
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bool Operand::getIndex() const { return Index; }
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unsigned Operand::getIndex() const {
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assert(Index >= 0 && "Index must be set");
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return Index;
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}
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bool Operand::isExplicit() const { return Info; }
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@ -57,13 +60,15 @@ bool Operand::isImmediate() const {
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getExplicitOperandInfo().OperandType == llvm::MCOI::OPERAND_IMMEDIATE;
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}
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int Operand::getTiedToIndex() const {
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assert(isTied());
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unsigned Operand::getTiedToIndex() const {
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assert(isTied() && "Operand must be tied to get the tied index");
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assert(TiedToIndex >= 0 && "TiedToIndex must be set");
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return TiedToIndex;
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}
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int Operand::getVariableIndex() const {
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assert(isVariable());
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unsigned Operand::getVariableIndex() const {
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assert(isVariable() && "Operand must be variable to get the Variable index");
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assert(VariableIndex >= 0 && "VariableIndex must be set");
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return VariableIndex;
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}
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@ -179,6 +184,51 @@ bool Instruction::hasAliasingRegisters() const {
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return AllDefRegs.anyCommon(AllUseRegs);
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}
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void Instruction::Dump(const llvm::MCRegisterInfo &RegInfo,
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llvm::raw_ostream &Stream) const {
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for (const auto &Op : Operands) {
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Stream << "- Op" << Op.getIndex();
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if (Op.isExplicit())
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Stream << " Explicit";
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if (Op.isImplicit())
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Stream << " Implicit";
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if (Op.isUse())
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Stream << " Use";
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if (Op.isDef())
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Stream << " Def";
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if (Op.isImmediate())
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Stream << " Immediate";
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if (Op.isMemory())
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Stream << " Memory";
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if (Op.isReg()) {
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if (Op.isImplicitReg())
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Stream << " Reg(" << RegInfo.getName(Op.getImplicitReg()) << ")";
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else
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Stream << " RegClass("
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<< RegInfo.getRegClassName(
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&RegInfo.getRegClass(Op.Info->RegClass))
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<< ")";
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}
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if (Op.isTied())
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Stream << " TiedToOp" << Op.getTiedToIndex();
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Stream << "\n";
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}
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for (const auto &Var : Variables) {
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Stream << "- Var" << Var.getIndex();
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for (auto OperandIndex : Var.TiedOperands)
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Stream << " Op" << OperandIndex;
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Stream << "\n";
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}
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if (hasMemoryOperands())
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Stream << "- hasMemoryOperands\n";
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if (hasAliasingImplicitRegisters())
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Stream << "- hasAliasingImplicitRegisters (execution is always serial)\n";
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if (hasTiedRegisters())
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Stream << "- hasTiedRegisters (execution is always serial)\n";
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if (hasAliasingRegisters())
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Stream << "- hasAliasingRegisters\n";
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}
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bool RegisterOperandAssignment::
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operator==(const RegisterOperandAssignment &Other) const {
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return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);
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@ -62,7 +62,6 @@ struct Variable {
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// - VariableIndex: the index of the Variable holding the value for this Operand
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// or -1 if this operand is implicit.
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struct Operand {
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bool getIndex() const;
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bool isExplicit() const;
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bool isImplicit() const;
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bool isImplicitReg() const;
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@ -73,8 +72,9 @@ struct Operand {
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bool isVariable() const;
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bool isMemory() const;
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bool isImmediate() const;
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int getTiedToIndex() const;
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int getVariableIndex() const;
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unsigned getIndex() const;
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unsigned getTiedToIndex() const;
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unsigned getVariableIndex() const;
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unsigned getImplicitReg() const;
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const RegisterAliasingTracker &getRegisterAliasing() const;
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const llvm::MCOperandInfo &getExplicitOperandInfo() const;
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@ -118,6 +118,10 @@ struct Instruction {
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// aliasing Use and Def registers.
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bool hasAliasingRegisters() const;
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// Convenient function to help with debugging.
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void Dump(const llvm::MCRegisterInfo &RegInfo,
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llvm::raw_ostream &Stream) const;
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const llvm::MCInstrDesc *Description; // Never nullptr.
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llvm::SmallVector<Operand, 8> Operands;
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llvm::SmallVector<Variable, 4> Variables;
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