[llvm-exegesis] Remove unused variable, add more semantic to Instruction.

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D53062

llvm-svn: 344127
This commit is contained in:
Guillaume Chatelet 2018-10-10 09:12:36 +00:00
parent e0f56f3bb6
commit a12bd277bd
2 changed files with 31 additions and 10 deletions

View File

@ -175,6 +175,18 @@ bool Instruction::hasAliasingImplicitRegisters() const {
return ImplDefRegs.anyCommon(ImplUseRegs);
}
bool Instruction::hasAliasingImplicitRegistersThrough(
const Instruction &OtherInstr) const {
return ImplDefRegs.anyCommon(OtherInstr.ImplUseRegs) &&
OtherInstr.ImplDefRegs.anyCommon(ImplUseRegs);
}
bool Instruction::hasAliasingRegistersThrough(
const Instruction &OtherInstr) const {
return AllDefRegs.anyCommon(OtherInstr.AllUseRegs) &&
OtherInstr.AllDefRegs.anyCommon(AllUseRegs);
}
bool Instruction::hasTiedRegisters() const {
return llvm::any_of(
Variables, [](const Variable &Var) { return Var.hasTiedOperands(); });
@ -215,8 +227,10 @@ void Instruction::dump(const llvm::MCRegisterInfo &RegInfo,
}
for (const auto &Var : Variables) {
Stream << "- Var" << Var.getIndex();
Stream << " (";
for (auto OperandIndex : Var.TiedOperands)
Stream << " Op" << OperandIndex;
Stream << "Op" << OperandIndex;
Stream << ")";
Stream << "\n";
}
if (hasMemoryOperands())

View File

@ -44,7 +44,7 @@ struct Variable {
// The indices of the operands tied to this Variable.
llvm::SmallVector<unsigned, 2> TiedOperands;
llvm::MCOperand AssignedValue;
// The index of this Variable in Instruction.Variables and its associated
// Value in InstructionBuilder.VariableValues.
int Index = -1;
@ -99,25 +99,32 @@ struct Instruction {
// In case the Variable is tied, the primary (i.e. Def) Operand is returned.
const Operand &getPrimaryOperand(const Variable &Var) const;
// Returns whether this instruction has Memory Operands.
// Repeating this instruction executes sequentially with an instruction that
// reads or write the same memory region.
bool hasMemoryOperands() const;
// Whether this instruction is self aliasing through its tied registers.
// Repeating this instruction is guaranteed to executes sequentially.
bool hasTiedRegisters() const;
// Whether this instruction is self aliasing through its implicit registers.
// Repeating this instruction is guaranteed to executes sequentially.
bool hasAliasingImplicitRegisters() const;
// Whether this instruction is self aliasing through its tied registers.
// Repeating this instruction is guaranteed to executes sequentially.
bool hasTiedRegisters() const;
// Whether this instruction is self aliasing through some registers.
// Repeating this instruction may execute sequentially by picking aliasing
// Use and Def registers. It may also execute in parallel by picking non
// aliasing Use and Def registers.
bool hasAliasingRegisters() const;
// Whether this instruction's implicit registers alias with OtherInstr's
// implicit registers.
bool hasAliasingImplicitRegistersThrough(const Instruction &OtherInstr) const;
// Whether this instruction's registers alias with OtherInstr's registers.
bool hasAliasingRegistersThrough(const Instruction &OtherInstr) const;
// Returns whether this instruction has Memory Operands.
// Repeating this instruction executes sequentially with an instruction that
// reads or write the same memory region.
bool hasMemoryOperands() const;
// Convenient function to help with debugging.
void dump(const llvm::MCRegisterInfo &RegInfo,
llvm::raw_ostream &Stream) const;