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https://github.com/RPCS3/llvm-mirror.git
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Thumb2 and ARM add/subtract with carry fixes.
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). llvm-svn: 130048
This commit is contained in:
Andrew Trick
parent
db92825944
commit
a130d110d1
@ -5040,6 +5040,72 @@ MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
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llvm_unreachable("Expecting a BB with two successors!");
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}
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// FIXME: This opcode table should obviously be expressed in the target
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// description. We probably just need a "machine opcode" value in the pseudo
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// instruction. But the ideal solution maybe to simply remove the "S" version
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// of the opcode altogether.
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struct AddSubFlagsOpcodePair {
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unsigned PseudoOpc;
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unsigned MachineOpc;
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};
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static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
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{ARM::ADCSri, ARM::ADCri},
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{ARM::ADCSrr, ARM::ADCrr},
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{ARM::ADCSrs, ARM::ADCrs},
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{ARM::SBCSri, ARM::SBCri},
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{ARM::SBCSrr, ARM::SBCrr},
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{ARM::SBCSrs, ARM::SBCrs},
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{ARM::RSBSri, ARM::RSBri},
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{ARM::RSBSrr, ARM::RSBrr},
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{ARM::RSBSrs, ARM::RSBrs},
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{ARM::RSCSri, ARM::RSCri},
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{ARM::RSCSrs, ARM::RSCrs},
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{ARM::t2ADCSri, ARM::t2ADCri},
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{ARM::t2ADCSrr, ARM::t2ADCrr},
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{ARM::t2ADCSrs, ARM::t2ADCrs},
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{ARM::t2SBCSri, ARM::t2SBCri},
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{ARM::t2SBCSrr, ARM::t2SBCrr},
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{ARM::t2SBCSrs, ARM::t2SBCrs},
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{ARM::t2RSBSri, ARM::t2RSBri},
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{ARM::t2RSBSrs, ARM::t2RSBrs},
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};
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// Convert and Add or Subtract with Carry and Flags to a generic opcode with
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// CPSR<def> operand. e.g. ADCS (...) -> ADC (... CPSR<def>).
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//
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// FIXME: Somewhere we should assert that CPSR<def> is in the correct
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// position to be recognized by the target descrition as the 'S' bit.
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bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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unsigned OldOpc = MI->getOpcode();
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unsigned NewOpc = 0;
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// This is only called for instructions that need remapping, so iterating over
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// the tiny opcode table is not costly.
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static const int NPairs =
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sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
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for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
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*End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) {
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if (OldOpc == Pair->PseudoOpc) {
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NewOpc = Pair->MachineOpc;
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break;
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}
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}
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if (!NewOpc)
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return false;
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
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for (unsigned i = 0; i < MI->getNumOperands(); ++i)
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MIB.addOperand(MI->getOperand(i));
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AddDefaultPred(MIB);
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MIB.addReg(ARM::CPSR, RegState::Define); // S bit
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MI->eraseFromParent();
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return true;
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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@ -5047,10 +5113,13 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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switch (MI->getOpcode()) {
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default:
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default: {
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if (RemapAddSubWithFlags(MI, BB))
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return BB;
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MI->dump();
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llvm_unreachable("Unexpected instr type to insert");
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}
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case ARM::ATOMIC_LOAD_ADD_I8:
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return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
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case ARM::ATOMIC_LOAD_ADD_I16:
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@ -5101,68 +5170,6 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
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case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
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case ARM::ADCSSri:
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case ARM::ADCSSrr:
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case ARM::ADCSSrs:
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case ARM::SBCSSri:
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case ARM::SBCSSrr:
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case ARM::SBCSSrs:
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case ARM::RSBSri:
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case ARM::RSBSrr:
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case ARM::RSBSrs:
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case ARM::RSCSri:
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case ARM::RSCSrs: {
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unsigned OldOpc = MI->getOpcode();
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unsigned Opc = 0;
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switch (OldOpc) {
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case ARM::ADCSSrr:
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Opc = ARM::ADCrr;
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break;
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case ARM::ADCSSri:
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Opc = ARM::ADCri;
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break;
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case ARM::ADCSSrs:
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Opc = ARM::ADCrs;
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break;
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case ARM::SBCSSrr:
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Opc = ARM::SBCrr;
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break;
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case ARM::SBCSSri:
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Opc = ARM::SBCri;
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break;
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case ARM::SBCSSrs:
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Opc = ARM::SBCrs;
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break;
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case ARM::RSBSri:
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Opc = ARM::RSBri;
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break;
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case ARM::RSBSrr:
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Opc = ARM::RSBrr;
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break;
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case ARM::RSBSrs:
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Opc = ARM::RSBrs;
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break;
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case ARM::RSCSri:
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Opc = ARM::RSCri;
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break;
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case ARM::RSCSrs:
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Opc = ARM::RSCrs;
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break;
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default:
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llvm_unreachable("Unknown opcode?");
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}
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MachineInstrBuilder MIB =
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BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(Opc));
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for (unsigned i = 0; i < MI->getNumOperands(); ++i)
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MIB.addOperand(MI->getOperand(i));
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AddDefaultPred(MIB);
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MIB.addReg(ARM::CPSR, RegState::Define); // S bit
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MI->eraseFromParent();
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return BB;
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}
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case ARM::tMOVCCr_pseudo: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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@ -5474,7 +5481,7 @@ static SDValue PerformANDCombine(SDNode *N,
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if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return SDValue();
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APInt SplatBits, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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@ -5510,7 +5517,7 @@ static SDValue PerformORCombine(SDNode *N,
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if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return SDValue();
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APInt SplatBits, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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@ -485,6 +485,7 @@ namespace llvm {
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unsigned Size,
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unsigned BinOpcode) const;
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bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
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};
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enum NEONModImmType {
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@ -940,16 +940,16 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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// NOTE: CPSR def omitted because it will be handled by the custom inserter.
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let usesCustomInserter = 1 in {
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multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
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def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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Size4Bytes, IIC_iALUi,
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def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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Size4Bytes, IIC_iALUi,
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[(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
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def Srr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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Size4Bytes, IIC_iALUr,
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def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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Size4Bytes, IIC_iALUr,
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[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
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let isCommutable = Commutable;
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}
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def Srs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
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Size4Bytes, IIC_iALUsr,
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def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
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Size4Bytes, IIC_iALUsr,
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[(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
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}
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}
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@ -2330,8 +2330,10 @@ def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
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// The with-carry-in form matches bitwise not instead of the negation.
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// Effectively, the inverse interpretation of the carry flag already accounts
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// for part of the negation.
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def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
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def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
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(SBCri GPR:$src, so_imm_not:$imm)>;
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def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
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(SBCSri GPR:$src, so_imm_not:$imm)>;
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// Note: These are implemented in C++ code, because they have to generate
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// ADD/SUBrs instructions, which use a complex pattern that a xform function
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@ -681,49 +681,27 @@ multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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let Inst{24-21} = opcod;
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}
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}
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}
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// Carry setting variants
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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// NOTE: CPSR def omitted because it will be handled by the custom inserter.
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let usesCustomInserter = 1 in {
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multiclass T2I_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
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// shifted imm
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def ri : T2sTwoRegImm<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
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opc, "\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
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Requires<[IsThumb2]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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let Inst{20} = 1; // The S bit.
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let Inst{15} = 0;
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}
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def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
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Size4Bytes, IIC_iALUi,
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[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>;
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// register
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def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
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opc, ".w\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
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Requires<[IsThumb2]> {
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def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
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Size4Bytes, IIC_iALUr,
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[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
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let isCommutable = Commutable;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{20} = 1; // The S bit.
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let Inst{14-12} = 0b000; // imm3
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let Inst{7-6} = 0b00; // imm2
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let Inst{5-4} = 0b00; // type
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}
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// shifted register
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def rs : T2sTwoRegShiftedReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
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IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
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Requires<[IsThumb2]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{20} = 1; // The S bit.
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}
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}
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def rs : t2PseudoInst<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
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Size4Bytes, IIC_iALUsi,
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[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>;
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}
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}
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@ -1803,10 +1781,8 @@ defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
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BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
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defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
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BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
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defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
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BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
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defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
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BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
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defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
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defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
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// RSB
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defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
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@ -1837,9 +1813,14 @@ def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
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// Effectively, the inverse interpretation of the carry flag already accounts
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// for part of the negation.
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let AddedComplexity = 1 in
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def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
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def : T2Pat<(adde_dead_carry rGPR:$src, imm0_255_not:$imm),
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(t2SBCri rGPR:$src, imm0_255_not:$imm)>;
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def : T2Pat<(adde_dead_carry rGPR:$src, t2_so_imm_not:$imm),
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(t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
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let AddedComplexity = 1 in
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def : T2Pat<(adde_live_carry rGPR:$src, imm0_255_not:$imm),
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(t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
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def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
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def : T2Pat<(adde_live_carry rGPR:$src, t2_so_imm_not:$imm),
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(t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
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// Select Bytes -- for disassembly only
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@ -19,3 +19,20 @@ entry:
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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}
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; add with live carry
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define i64 @f3(i32 %al, i32 %bl) {
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; CHECK: f3:
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; CHECK: adds r
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; CHECK: adcs r
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; CHECK: adc r
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entry:
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; unsigned wide add
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%aw = zext i32 %al to i64
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%bw = zext i32 %bl to i64
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%cw = add i64 %aw, %bw
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; ch == carry bit
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%ch = lshr i64 %cw, 32
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%dw = add i64 %ch, %bw
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ret i64 %dw
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}
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@ -52,3 +52,18 @@ define i64 @f6(i64 %a) {
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ret i64 %tmp
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}
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; Example from numerics code that manually computes wider-than-64 values.
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;
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; CHECK: _livecarry:
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; CHECK: adds
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; CHECK: adcs
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; CHECK: adc
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define i64 @livecarry(i64 %carry, i32 %digit) nounwind {
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%ch = lshr i64 %carry, 32
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%cl = and i64 %carry, 4294967295
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%truncdigit = zext i32 %digit to i64
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%prod = add i64 %cl, %truncdigit
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%ph = lshr i64 %prod, 32
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%carryresult = add i64 %ch, %ph
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ret i64 %carryresult
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}
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@ -4,7 +4,7 @@
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define i64 @f1(i64 %a) {
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; CHECK: f1
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; CHECK: subs r0, #171
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; CHECK: adc r1, r1, #-1
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 171
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ret i64 %tmp
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}
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@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
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define i64 @f2(i64 %a) {
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; CHECK: f2
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; CHECK: subs.w r0, r0, #1179666
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; CHECK: adc r1, r1, #-1
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 1179666
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ret i64 %tmp
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}
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@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
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define i64 @f3(i64 %a) {
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; CHECK: f3
|
||||
; CHECK: subs.w r0, r0, #872428544
|
||||
; CHECK: adc r1, r1, #-1
|
||||
; CHECK: sbc r1, r1, #0
|
||||
%tmp = sub i64 %a, 872428544
|
||||
ret i64 %tmp
|
||||
}
|
||||
@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
|
||||
define i64 @f4(i64 %a) {
|
||||
; CHECK: f4
|
||||
; CHECK: subs.w r0, r0, #1448498774
|
||||
; CHECK: adc r1, r1, #-1
|
||||
; CHECK: sbc r1, r1, #0
|
||||
%tmp = sub i64 %a, 1448498774
|
||||
ret i64 %tmp
|
||||
}
|
||||
@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
|
||||
define i64 @f5(i64 %a) {
|
||||
; CHECK: f5
|
||||
; CHECK: subs.w r0, r0, #66846720
|
||||
; CHECK: adc r1, r1, #-1
|
||||
; CHECK: sbc r1, r1, #0
|
||||
%tmp = sub i64 %a, 66846720
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
@ -1,9 +1,10 @@
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2 -mattr=+32bit | FileCheck %s
|
||||
|
||||
define i64 @f1(i64 %a, i64 %b) {
|
||||
; CHECK: f1:
|
||||
; CHECK: subs r0, r0, r2
|
||||
; CHECK: sbcs r1, r3
|
||||
; CHECK: subs.w r0, r0, r2
|
||||
; To test dead_carry, +32bit prevents sbc conveting to 16-bit sbcs
|
||||
; CHECK: sbc.w r1, r1, r3
|
||||
%tmp = sub i64 %a, %b
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user