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Get rid of the last non-DebugLoc versions of getNode!

Browse Source 
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base.  There's no
sensible way to associate debug info with these.  I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. 
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.

llvm-svn: 63992
This commit is contained in:
Dale Johannesen 2009-02-07 00:55:49 +00:00
parent 8437b9efa1
commit a259483aae
16 changed files with 103 additions and 85 deletions
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10
include/llvm/CodeGen/SelectionDAG.h
View File

@ -407,11 +407,15 @@ public:
return getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), VT);
}
/// getGLOBAL_OFFSET_TABLE - Return a GLOBAL_OFFSET_TABLE node. This does
/// not have a useful DebugLoc.
SDValue getGLOBAL_OFFSET_TABLE(MVT VT) {
return getNode(ISD::GLOBAL_OFFSET_TABLE, DebugLoc::getUnknownLoc(), VT);
}
/// getNode - Gets or creates the specified node.
///
SDValue getNode(unsigned Opcode, MVT VT);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT);
SDValue getNode(unsigned Opcode, MVT VT, SDValue N);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
@ -421,8 +425,6 @@ public:
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
SDValue N5);
SDValue getNode(unsigned Opcode, MVT VT,
const SDUse *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
const SDUse *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,

6
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -2189,7 +2189,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
Tmp4 = LegalizeOp(Tmp1.getValue(1));
break;
}
@ -3429,7 +3429,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// Select between the nabs and abs value based on the sign bit of
// the input.
Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
AbsVal),
AbsVal);
Result = LegalizeOp(Result);
@ -5987,7 +5987,7 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
case TargetLowering::Expand:
break; // This case is handled below.
case TargetLowering::Custom: {
SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
Source), DAG);
if (NV.getNode())
return LegalizeOp(NV);

2
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
View File

@ -1107,7 +1107,7 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
MVT::i64, Src);
LC = RTLIB::SINTTOFP_I64_PPCF128;
} else if (SrcVT.bitsLE(MVT::i128)) {
Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i128, Src);
Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
LC = RTLIB::SINTTOFP_I128_PPCF128;
}
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");

11
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -246,10 +246,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
MVT VT = N->getValueType(0);
// FIXME there is no actual debug info here
DebugLoc dl = N->getDebugLoc();
// Zero extend things like i1, sign extend everything else. It shouldn't
// matter in theory which one we pick, but this tends to give better code?
unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
SDValue(N, 0));
assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
return Result;
@ -270,11 +272,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
// Zero extend to the promoted type and do the count there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
DebugLoc dl = N->getDebugLoc();
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
Op = DAG.getNode(ISD::CTLZ, NVT, Op);
Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
// Subtract off the extra leading bits in the bigger type.
return DAG.getNode(ISD::SUB, N->getDebugLoc(), NVT, Op,
return DAG.getNode(ISD::SUB, dl, NVT, Op,
DAG.getConstant(NVT.getSizeInBits() -
OVT.getSizeInBits(), NVT));
}
@ -1408,7 +1411,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
MVT NVT = Lo.getValueType();
Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
Hi = DAG.getConstant(0, NVT);
}

15
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1280,7 +1280,7 @@ SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
if (OpTy == ShTy || OpTy.isVector()) return Op;
ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
return getNode(Opcode, ShTy, Op);
return getNode(Opcode, Op.getDebugLoc(), ShTy, Op);
}
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
@ -2158,10 +2158,6 @@ SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
/// getNode - Gets or creates the specified node.
///
SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) {
return getNode(Opcode, DebugLoc::getUnknownLoc(), VT);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
@ -2179,10 +2175,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
return SDValue(N, 0);
}
SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) {
return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Operand);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
MVT VT, SDValue Operand) {
// Constant fold unary operations with an integer constant operand.
@ -3690,11 +3682,6 @@ SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl,
return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
}
SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
const SDUse *Ops, unsigned NumOps) {
return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
const SDUse *Ops, unsigned NumOps) {
switch (NumOps) {

2
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -692,7 +692,7 @@ unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const {
if (usesGlobalOffsetTable())
return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
return Table;
}

27
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -538,7 +538,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
@ -557,7 +557,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
@ -718,6 +718,8 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
// into MOVi.
static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
// FIXME there is no actual debug info here
DebugLoc dl = Op.getDebugLoc();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
SDValue Res;
if (CP->isMachineConstantPoolEntry())
@ -726,7 +728,7 @@ static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
else
Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
CP->getAlignment());
return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model
@ -740,7 +742,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "tlsgd", true);
SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
SDValue Chain = Argument.getValue(1);
@ -781,7 +783,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "gottpoff", true);
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
Chain = Offset.getValue(1);
@ -794,7 +796,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
}
@ -828,18 +830,18 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
if (!UseGOTOFF)
Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
return Result;
} else {
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
}
}
@ -874,7 +876,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
Kind, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
}
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
@ -900,7 +902,7 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
ARMPCLabelIndex,
ARMCP::CPValue, PCAdj);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
@ -912,7 +914,8 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::arm_thread_pointer:
return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
return DAG.getNode(ARMISD::THREAD_POINTER, DebugLoc::getUnknownLoc(),
PtrVT);
}
}

14
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -190,7 +190,7 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
return Lo;
}
@ -305,6 +305,7 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), dl, Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr,
DebugLoc::getUnknownLoc(),
MVT::i64),
SDValue());
switch (Op.getNumOperands()) {
@ -517,7 +518,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
// FIXME there isn't really any debug info here
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
return Lo;
}
@ -532,18 +533,18 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
if (GV->hasLocalLinkage()) {
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
return Lo;
} else
return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::ExternalSymbol: {
return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
->getSymbol(), MVT::i64),
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::UREM:
@ -622,7 +623,8 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SA2, NULL, 0, MVT::i32);
}
case ISD::RETURNADDR:
return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
MVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
}

6
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -922,7 +922,7 @@ LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
SDValue T = DAG.getConstant(dbits, MVT::i64);
SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Tvec));
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec));
}
return SDValue();
@ -2536,7 +2536,7 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
ISD::SETGT));
}
SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, rhs);
SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs);
SDValue rhsHi32 =
DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT,
@ -2677,7 +2677,7 @@ static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
PromoteScalar, PromoteScalar, shufMask);
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
DAG.getNode(ISD::BIT_CONVERT, VecVT, truncShuffle));
DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, truncShuffle));
}
return SDValue(); // Leave the truncate unmolested

4
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -484,7 +484,7 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
// %gp_rel relocation
if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, 1, Ops, 1);
SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
}
// %hi/%lo relocation
@ -557,7 +557,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG)
//if (!Subtarget->hasABICall() &&
// IsInSmallSection(getTargetData()->getTypePaddedSize(C->getType()))) {
// SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
// SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
// SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
// ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
//} else { // %hi/%lo relocation
SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);

14
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -328,7 +328,7 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
DebugLoc dl = N->getDebugLoc();
SDValue PtrLo, PtrHi;
LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset);
LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
if (ValueType == MVT::i8) {
return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
@ -556,7 +556,7 @@ PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
void PIC16TargetLowering:: LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
SDValue &Lo, SDValue &Hi,
unsigned &Offset) {
unsigned &Offset, DebugLoc dl) {
// Offset, by default, should be 0
Offset = 0;
@ -615,8 +615,8 @@ void PIC16TargetLowering:: LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
GetExpandedParts(Ptr, DAG, Lo, Hi);
// Put the hi and lo parts into FSR.
Lo = DAG.getNode(PIC16ISD::MTLO, MVT::i8, Lo);
Hi = DAG.getNode(PIC16ISD::MTHI, MVT::i8, Hi);
Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
return;
}
@ -648,7 +648,7 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
// Legalize direct/indirect addresses. This will give the lo and hi parts
// of the address and the offset.
LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset);
LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
// Load from the pointer (direct address or FSR)
VT = N->getValueType(0);
@ -897,7 +897,7 @@ PIC16TargetLowering::LowerCallArguments(SDValue Op, SDValue Chain,
SDValue PtrLo, PtrHi;
unsigned AddressOffset;
int StoreOffset = 0;
LegalizeAddress(FrameAddress, DAG, PtrLo, PtrHi, AddressOffset);
LegalizeAddress(FrameAddress, DAG, PtrLo, PtrHi, AddressOffset, dl);
SDValue StoreRet;
std::vector<SDValue> Ops;
@ -954,7 +954,7 @@ PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain,
// Legalize the address before use
SDValue LdLo, LdHi;
unsigned LdOffset;
LegalizeAddress(FrameAddress, DAG, LdLo, LdHi, LdOffset);
LegalizeAddress(FrameAddress, DAG, LdLo, LdHi, LdOffset, dl);
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
SDValue LoadRet;

2
lib/Target/PIC16/PIC16ISelLowering.h
View File

@ -138,7 +138,7 @@ namespace llvm {
// addresses need Banksel and Indirect addresses need to be loaded to
// FSR first. Handle address specific cases here.
void LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Chain,
SDValue &NewPtr, unsigned &Offset);
SDValue &NewPtr, unsigned &Offset, DebugLoc dl);
// FrameIndex should be broken down into ExternalSymbol and FrameOffset.
void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES,

9
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1095,7 +1095,8 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
DAG.getNode(PPCISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
@ -1127,7 +1128,8 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
DAG.getNode(PPCISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
@ -1167,7 +1169,8 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
DAG.getNode(PPCISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);

10
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -756,17 +756,19 @@ static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
}
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// Convert the fp value to integer in an FP register.
assert(Op.getValueType() == MVT::i32);
Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
}
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
assert(Op.getOperand(0).getValueType() == MVT::i32);
SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
}
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {

42
lib/Target/X86/X86ISelLowering.cpp
View File

@ -900,9 +900,12 @@ X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const {
if (usesGlobalOffsetTable())
return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
if (!Subtarget->isPICStyleRIPRel())
return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
// This doesn't have DebugLoc associated with it, but is not really the
// same as a Register.
return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
getPointerTy());
return Table;
}
@ -1663,7 +1666,9 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
// GOT pointer.
if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
DAG.getNode(X86ISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(),
getPointerTy()),
InFlag);
InFlag = Chain.getValue(1);
}
@ -3392,7 +3397,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
unsigned NumBits = VT.getSizeInBits();
return getVShift(true, VT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
VT, Op.getOperand(1)),
NumBits/2, DAG, *this, dl);
}
@ -4511,12 +4517,14 @@ X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
getPointerTy(),
CP->getAlignment());
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
!Subtarget->isPICStyleRIPRel()) {
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
DAG.getNode(X86ISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(),
getPointerTy()),
Result);
}
@ -4539,7 +4547,7 @@ X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
Offset = 0;
} else
Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (IsPic && !Subtarget->isPICStyleRIPRel()) {
@ -4581,6 +4589,7 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
DAG.getNode(X86ISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(),
PtrVT), InFlag);
InFlag = Chain.getValue(1);
@ -4652,13 +4661,14 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
const MVT PtrVT) {
DebugLoc dl = GA->getDebugLoc();
// Get the Thread Pointer
SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
DebugLoc::getUnknownLoc(), PtrVT);
// emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
// exec)
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
GA->getValueType(0),
GA->getOffset());
SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
@ -4694,12 +4704,14 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
!Subtarget->isPICStyleRIPRel()) {
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
DAG.getNode(X86ISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(),
getPointerTy()),
Result);
}
@ -4711,12 +4723,14 @@ SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
// FIXME there isn't really any debug into here
DebugLoc dl = JT->getDebugLoc();
SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
!Subtarget->isPICStyleRIPRel()) {
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
DAG.getNode(X86ISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(),
getPointerTy()),
Result);
}
@ -6371,7 +6385,7 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode((VT.getSizeInBits() < 16 ?
ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
}
SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {

14
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -204,8 +204,10 @@ LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
SDValue XCoreTargetLowering::
getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG)
{
// FIXME there is no actual debug info here
DebugLoc dl = GA.getDebugLoc();
if (isa<Function>(GV)) {
return DAG.getNode(XCoreISD::PCRelativeWrapper, MVT::i32, GA);
return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
} else if (!Subtarget.isXS1A()) {
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
if (!GVar) {
@ -215,10 +217,10 @@ getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG)
}
bool isConst = GVar && GVar->isConstant();
if (isConst) {
return DAG.getNode(XCoreISD::CPRelativeWrapper, MVT::i32, GA);
return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
}
}
return DAG.getNode(XCoreISD::DPRelativeWrapper, MVT::i32, GA);
return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
}
SDValue XCoreTargetLowering::
@ -232,8 +234,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
return getGlobalAddressWrapper(GA, GV, DAG);
}
static inline SDValue BuildGetId(SelectionDAG &DAG) {
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::i32,
static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
}
@ -269,7 +271,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
const TargetData *TD = TM.getTargetData();
unsigned Size = TD->getTypePaddedSize(Ty);
SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG),
SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
DAG.getConstant(Size, MVT::i32));
return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
}