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[ARM] Find VPT implicitly predicated by VCTP
On failing to find a VCTP in the list of instructions that explicitly predicate the entry of a VPT block, inspect whether the block is controlled via VPT which is implicitly predicated due to it's predicated operand(s). Differential Revision: https://reviews.llvm.org/D87819
This commit is contained in:
Sam Parker
parent
919066e494
commit
a28cbccef7
@ -433,7 +433,6 @@ MachineInstr *ReachingDefAnalysis::getUniqueReachingMIDef(MachineInstr *MI,
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if (LocalDef && InstIds.lookup(LocalDef) < InstIds.lookup(MI))
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return LocalDef;
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SmallPtrSet<MachineBasicBlock*, 4> VisitedBBs;
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SmallPtrSet<MachineInstr*, 2> Incoming;
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MachineBasicBlock *Parent = MI->getParent();
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for (auto *Pred : Parent->predecessors())
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@ -256,12 +256,54 @@ namespace {
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return isPredicatedOnVCTP(Insts.front(), Exclusive);
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}
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static bool isValid() {
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// If this block begins with a VPT, we can check whether it's using
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// at least one predicated input(s), as well as possible loop invariant
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// which would result in it being implicitly predicated.
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static bool hasImplicitlyValidVPT(VPTState &Block,
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ReachingDefAnalysis &RDA) {
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SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
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MachineInstr *VPT = Insts.front();
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assert(isVPTOpcode(VPT->getOpcode()) &&
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"Expected VPT block to begin with VPT/VPST");
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if (VPT->getOpcode() == ARM::MVE_VPST)
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return false;
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auto IsOperandPredicated = [&](MachineInstr *MI, unsigned Idx) {
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MachineInstr *Op = RDA.getMIOperand(MI, MI->getOperand(Idx));
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return Op && PredicatedInsts.count(Op) && isPredicatedOnVCTP(Op);
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};
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auto IsOperandInvariant = [&](MachineInstr *MI, unsigned Idx) {
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MachineOperand &MO = MI->getOperand(Idx);
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if (!MO.isReg() || !MO.getReg())
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return true;
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SmallPtrSet<MachineInstr *, 2> Defs;
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RDA.getGlobalReachingDefs(MI, MO.getReg(), Defs);
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if (Defs.empty())
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return true;
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for (auto *Def : Defs)
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if (Def->getParent() == VPT->getParent())
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return false;
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return true;
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};
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// Check that at least one of the operands is directly predicated on a
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// vctp and allow an invariant value too.
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return (IsOperandPredicated(VPT, 1) || IsOperandPredicated(VPT, 2)) &&
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(IsOperandPredicated(VPT, 1) || IsOperandInvariant(VPT, 1)) &&
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(IsOperandPredicated(VPT, 2) || IsOperandInvariant(VPT, 2));
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}
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static bool isValid(ReachingDefAnalysis &RDA) {
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// All predication within the loop should be based on vctp. If the block
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// isn't predicated on entry, check whether the vctp is within the block
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// and that all other instructions are then predicated on it.
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for (auto &Block : Blocks) {
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if (isEntryPredicatedOnVCTP(Block))
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if (isEntryPredicatedOnVCTP(Block, false) ||
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hasImplicitlyValidVPT(Block, RDA))
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continue;
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SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
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@ -517,7 +559,7 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) {
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return false;
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}
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if (!VPTState::isValid())
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if (!VPTState::isValid(RDA))
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return false;
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if (!ValidateLiveOuts()) {
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@ -7,23 +7,13 @@ define void @remat_vctp(i32* %arg, i32* %arg1, i32* %arg2, i32* %arg3, i32* %arg
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; CHECK-NEXT: push {r4, r5, r7, lr}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: ldrd r5, r12, [sp, #80]
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; CHECK-NEXT: cmp.w r12, #4
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; CHECK-NEXT: mov r4, r12
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; CHECK-NEXT: vmvn.i32 q0, #0x80000000
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; CHECK-NEXT: it ge
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; CHECK-NEXT: movge r4, #4
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; CHECK-NEXT: vmov.i32 q1, #0x3f
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; CHECK-NEXT: sub.w r4, r12, r4
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; CHECK-NEXT: vmov.i32 q2, #0x1
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; CHECK-NEXT: add.w lr, r4, #3
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; CHECK-NEXT: movs r4, #1
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; CHECK-NEXT: add.w lr, r4, lr, lsr #2
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: dlstp.32 lr, r12
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; CHECK-NEXT: .LBB0_1: @ %bb6
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vctp.32 r12
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vldrwt.u32 q4, [r1], #16
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; CHECK-NEXT: vldrw.u32 q4, [r1], #16
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; CHECK-NEXT: vabs.s32 q5, q4
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; CHECK-NEXT: vcls.s32 q3, q5
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; CHECK-NEXT: vshl.u32 q5, q5, q3
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@ -41,15 +31,11 @@ define void @remat_vctp(i32* %arg, i32* %arg1, i32* %arg2, i32* %arg3, i32* %arg
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; CHECK-NEXT: vqshl.s32 q5, q5, #1
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; CHECK-NEXT: vpt.s32 lt, q4, zr
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; CHECK-NEXT: vnegt.s32 q5, q5
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; CHECK-NEXT: vctp.32 r12
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; CHECK-NEXT: sub.w r12, r12, #4
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vldrwt.u32 q4, [r0], #16
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; CHECK-NEXT: vldrw.u32 q4, [r0], #16
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; CHECK-NEXT: vqrdmulh.s32 q4, q4, q5
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vstrwt.32 q4, [r2], #16
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; CHECK-NEXT: vstrwt.32 q3, [r3], #16
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; CHECK-NEXT: le lr, .LBB0_1
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; CHECK-NEXT: vstrw.32 q4, [r2], #16
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; CHECK-NEXT: vstrw.32 q3, [r3], #16
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; CHECK-NEXT: letp lr, .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %bb44
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: pop {r4, r5, r7, pc}
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@ -593,26 +593,17 @@ body: |
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; CHECK: bb.1.vector.ph:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
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; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
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; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
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; CHECK: $lr = t2DLS killed renamable $lr
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
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; CHECK: bb.2.vector.body:
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
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; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
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; CHECK: MVE_VPST 8, implicit $vpr
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; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr
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; CHECK: MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr
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; CHECK: liveins: $lr, $q0, $r0, $r2, $r3
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; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg
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; CHECK: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr
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; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr
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; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr
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; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr
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; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
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; CHECK: bb.3.for.cond.cleanup:
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; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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;
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