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[NFC][LV][TEST]: extend pr45679-fold-tail-by-masking.ll with -force-vector-width=1 -force-vector-interleave=4
Summary: Add -force-vector-width=1 -force-vector-interleave=4 to pr45679-fold-tail-by-masking.ll Author: anhtuyen (Anh Tuyen Tran) Reviewers: Ayal (Ayal Zaks) Reviewed By: Ayal (Ayal Zaks) Subscribers: rkruppe (Hanna Kruppe), llvm-commits, LLVM Tag: LLVM Differential Revision: https://reviews.llvm.org/D80446
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Anh Tuyen Tran
parent
f56c09c87f
commit
a3bbcd952c
@ -1,6 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-vectorize -force-vector-width=4 -S | FileCheck %s
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; RUN: opt < %s -loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S | FileCheck %s -check-prefix=VF2UF2
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; RUN: opt < %s -loop-vectorize -force-vector-width=1 -force-vector-interleave=4 -S | FileCheck %s -check-prefix=VF1UF4
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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@ -132,6 +133,63 @@ define void @pr45679(i32* %A) optsize {
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; VF2UF2: exit:
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; VF2UF2-NEXT: ret void
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;
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; VF1UF4-LABEL: @pr45679(
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; VF1UF4-NEXT: entry:
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; VF1UF4-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; VF1UF4: vector.ph:
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; VF1UF4-NEXT: br label [[VECTOR_BODY:%.*]]
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; VF1UF4: vector.body:
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; VF1UF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE9:%.*]] ]
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; VF1UF4-NEXT: [[INDUCTION:%.*]] = add i32 [[INDEX]], 0
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; VF1UF4-NEXT: [[INDUCTION1:%.*]] = add i32 [[INDEX]], 1
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; VF1UF4-NEXT: [[INDUCTION2:%.*]] = add i32 [[INDEX]], 2
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; VF1UF4-NEXT: [[INDUCTION3:%.*]] = add i32 [[INDEX]], 3
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; VF1UF4-NEXT: [[TMP0:%.*]] = icmp ule i32 [[INDUCTION]], 13
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; VF1UF4-NEXT: [[TMP1:%.*]] = icmp ule i32 [[INDUCTION1]], 13
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; VF1UF4-NEXT: [[TMP2:%.*]] = icmp ule i32 [[INDUCTION2]], 13
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; VF1UF4-NEXT: [[TMP3:%.*]] = icmp ule i32 [[INDUCTION3]], 13
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; VF1UF4-NEXT: br i1 [[TMP0]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
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; VF1UF4: pred.store.if:
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; VF1UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[INDUCTION]]
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; VF1UF4-NEXT: store i32 13, i32* [[TMP4]], align 1
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; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE]]
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; VF1UF4: pred.store.continue:
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; VF1UF4-NEXT: br i1 [[TMP1]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]]
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; VF1UF4: pred.store.if4:
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; VF1UF4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION1]]
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; VF1UF4-NEXT: store i32 13, i32* [[TMP5]], align 1
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; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE5]]
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; VF1UF4: pred.store.continue5:
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; VF1UF4-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7:%.*]]
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; VF1UF4: pred.store.if6:
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; VF1UF4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION2]]
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; VF1UF4-NEXT: store i32 13, i32* [[TMP6]], align 1
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; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE7]]
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; VF1UF4: pred.store.continue7:
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; VF1UF4-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9]]
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; VF1UF4: pred.store.if8:
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; VF1UF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION3]]
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; VF1UF4-NEXT: store i32 13, i32* [[TMP7]], align 1
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; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE9]]
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; VF1UF4: pred.store.continue9:
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; VF1UF4-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
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; VF1UF4-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16
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; VF1UF4-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]]
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; VF1UF4: middle.block:
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; VF1UF4-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
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; VF1UF4: scalar.ph:
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; VF1UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; VF1UF4-NEXT: br label [[LOOP:%.*]]
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; VF1UF4: loop:
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; VF1UF4-NEXT: [[RIV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[RIVPLUS1:%.*]], [[LOOP]] ]
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; VF1UF4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[RIV]]
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; VF1UF4-NEXT: store i32 13, i32* [[ARRAYIDX]], align 1
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; VF1UF4-NEXT: [[RIVPLUS1]] = add nuw nsw i32 [[RIV]], 1
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; VF1UF4-NEXT: [[COND:%.*]] = icmp eq i32 [[RIVPLUS1]], 14
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; VF1UF4-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]]
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; VF1UF4: exit:
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; VF1UF4-NEXT: ret void
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;
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entry:
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br label %loop
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@ -1,7 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-vectorize -force-vector-interleave=4 -pass-remarks='loop-vectorize' -disable-output -S 2>&1 | FileCheck %s --check-prefix=CHECK-REMARKS
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; RUN: opt < %s -loop-vectorize -force-vector-interleave=4 -S | FileCheck %s
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; RUN: opt < %s -loop-vectorize -force-vector-width=1 -force-vector-interleave=4 -S | FileCheck %s --check-prefix=CHECK-VF1
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; These tests are to check that fold-tail procedure produces correct scalar code when
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; loop-vectorization is only unrolling but not vectorizing.
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@ -110,80 +109,3 @@ for.body:
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%cond = icmp eq double* %ptr, %ptr2
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br i1 %cond, label %for.cond.cleanup, label %for.body
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}
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; The following testcase is extended from the test of https://reviews.llvm.org/D80085
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; Similar to two tests above, it is to check that fold-tail procedure produces correct scalar code when
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; loop-vectorization is only unrolling but not vectorizing.
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define void @pr45679(i32* %A) optsize {
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; CHECK-VF1-LABEL: @pr45679
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; CHECK-VF1-NEXT: entry:
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; CHECK-VF1-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK-VF1: vector.ph:
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; CHECK-VF1-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK-VF1: vector.body:
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; CHECK-VF1-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE9:%.*]] ]
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; CHECK-VF1-NEXT: [[INDUCTION:%.*]] = add i32 [[INDEX]], 0
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; CHECK-VF1-NEXT: [[INDUCTION1:%.*]] = add i32 [[INDEX]], 1
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; CHECK-VF1-NEXT: [[INDUCTION2:%.*]] = add i32 [[INDEX]], 2
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; CHECK-VF1-NEXT: [[INDUCTION3:%.*]] = add i32 [[INDEX]], 3
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; CHECK-VF1-NEXT: [[TMP0:%.*]] = icmp ule i32 [[INDUCTION]], 13
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; CHECK-VF1-NEXT: [[TMP1:%.*]] = icmp ule i32 [[INDUCTION1]], 13
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; CHECK-VF1-NEXT: [[TMP2:%.*]] = icmp ule i32 [[INDUCTION2]], 13
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; CHECK-VF1-NEXT: [[TMP3:%.*]] = icmp ule i32 [[INDUCTION3]], 13
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; CHECK-VF1-NEXT: br i1 [[TMP0]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
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; CHECK-VF1: pred.store.if:
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; CHECK-VF1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[INDUCTION]]
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; CHECK-VF1-NEXT: store i32 13, i32* [[TMP4]], align 1
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; CHECK-VF1-NEXT: br label [[PRED_STORE_CONTINUE]]
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; CHECK-VF1: pred.store.continue:
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; CHECK-VF1-NEXT: br i1 [[TMP1]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]]
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; CHECK-VF1: pred.store.if4:
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; CHECK-VF1-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION1]]
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; CHECK-VF1-NEXT: store i32 13, i32* [[TMP5]], align 1
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; CHECK-VF1-NEXT: br label [[PRED_STORE_CONTINUE5]]
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; CHECK-VF1: pred.store.continue5:
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; CHECK-VF1-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7:%.*]]
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; CHECK-VF1: pred.store.if6:
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; CHECK-VF1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION2]]
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; CHECK-VF1-NEXT: store i32 13, i32* [[TMP6]], align 1
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; CHECK-VF1-NEXT: br label [[PRED_STORE_CONTINUE7]]
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; CHECK-VF1: pred.store.continue7:
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; CHECK-VF1-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9]]
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; CHECK-VF1: pred.store.if8:
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; CHECK-VF1-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION3]]
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; CHECK-VF1-NEXT: store i32 13, i32* [[TMP7]], align 1
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; CHECK-VF1-NEXT: br label [[PRED_STORE_CONTINUE9]]
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; CHECK-VF1: pred.store.continue9:
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; CHECK-VF1-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
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; CHECK-VF1-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16
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; CHECK-VF1-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]]
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; CHECK-VF1: middle.block:
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; CHECK-VF1-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK-VF1: scalar.ph:
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; CHECK-VF1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-VF1-NEXT: br label [[LOOP:%.*]]
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; CHECK-VF1: loop:
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; CHECK-VF1-NEXT: [[RIV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[RIVPLUS1:%.*]], [[LOOP]] ]
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; CHECK-VF1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[RIV]]
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; CHECK-VF1-NEXT: store i32 13, i32* [[ARRAYIDX]], align 1
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; CHECK-VF1-NEXT: [[RIVPLUS1]] = add nuw nsw i32 [[RIV]], 1
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; CHECK-VF1-NEXT: [[COND:%.*]] = icmp eq i32 [[RIVPLUS1]], 14
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; CHECK-VF1-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]]
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; CHECK-VF1: exit:
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; CHECK-VF1-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%riv = phi i32 [ 0, %entry ], [ %rivPlus1, %loop ]
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%arrayidx = getelementptr inbounds i32, i32* %A, i32 %riv
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store i32 13, i32* %arrayidx, align 1
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%rivPlus1 = add nuw nsw i32 %riv, 1
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%cond = icmp eq i32 %rivPlus1, 14
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br i1 %cond, label %exit, label %loop
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exit:
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ret void
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}
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