RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-10 13:51:37 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[X86][SSE] Remove UNPCKL(SHUFFLE)->UNPCKH custom combine

Browse Source 
This can be achieved more generally by combineX86ShufflesRecursively.

llvm-svn: 342645
This commit is contained in:
Simon Pilgrim 2018-09-20 13:10:22 +00:00
parent 1303cd31cb
commit a44cd33adb
1 changed files with 0 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/Target/X86/X86ISelLowering.cpp
View File

@ -31087,40 +31087,6 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
Mask = getPSHUFShuffleMask(N); Mask = getPSHUFShuffleMask(N);
assert(Mask.size() == 4); assert(Mask.size() == 4);
break; break;
case X86ISD::UNPCKL: {
// Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
// which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
// moves upper half elements into the lower half part. For example:
//
// t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
// undef:v16i8
// t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
//
// will be combined to:
//
// t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
// This is only for 128-bit vectors. From SSE4.1 onward this combine may not
// happen due to advanced instructions.
if (!VT.is128BitVector())
return SDValue();
auto Op0 = N.getOperand(0);
auto Op1 = N.getOperand(1);
if (Op0.isUndef() && Op1.getOpcode() == ISD::VECTOR_SHUFFLE) {
ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
unsigned NumElts = VT.getVectorNumElements();
SmallVector<int, 8> ExpectedMask(NumElts, -1);
std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
NumElts / 2);
auto ShufOp = Op1.getOperand(0);
if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
}
return SDValue();
}
case X86ISD::MOVSD: case X86ISD::MOVSD:
case X86ISD::MOVSS: { case X86ISD::MOVSS: {
SDValue N0 = N.getOperand(0); SDValue N0 = N.getOperand(0);