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Added code for correct reordering of call arguments
llvm-svn: 1234
This commit is contained in:
Ruchira Sasanka
parent
3659e104ec
commit
a4a64f3755
@ -284,6 +284,10 @@ class UltraSparcRegInfo : public MachineRegInfo
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MachineInstr * cpCCR2IntMI(const unsigned IntReg) const;
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MachineInstr * cpInt2CCRMI(const unsigned IntReg) const;
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void OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
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vector<MachineInstr *> &OrdVec) const;
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public:
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@ -590,6 +590,8 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
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// Now color all args of the call instruction
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vector <MachineInstr *> AddedInstrnsBefore;
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unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
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for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
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@ -666,7 +668,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
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AdMI = cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, RegType );
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}
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CallAI->InstrnsBefore.push_back( AdMI ); // Now add the instruction
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AddedInstrnsBefore.push_back( AdMI ); // Now add the instruction
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}
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else { // LR is not colored (i.e., spilled)
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@ -681,7 +683,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
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AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
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UniArgReg, RegType );
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CallAI->InstrnsBefore.push_back( AdMI ); // Now add the instruction
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AddedInstrnsBefore.push_back( AdMI ); // Now add the instruction
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}
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else {
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@ -696,6 +698,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
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// above method since we cannot find LVSetBefore without the BB
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int TReg = PRA.getRegNotUsedByThisInst( LR->getRegClass(), CallMI );
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int TmpOff = PRA.mcInfo.pushTempValue(target,
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target.findOptimalStorageSize(LR->getType()));
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// getStackOffsets().getNewTmpPosOffFromFP();
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@ -715,19 +718,51 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
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TReg, RegType );
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Ad3 = cpReg2MemMI(TReg, getStackPointer(), argOffset, RegType );
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Ad4 = cpMem2RegMI(getFramePointer(), TmpOff, TReg, RegType );
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// We directly add to CallAI->InstrnsBefore instead of adding to
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// AddedInstrnsBefore since these instructions must not be
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// reordered.
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CallAI->InstrnsBefore.push_back( Ad1 );
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CallAI->InstrnsBefore.push_back( Ad2 );
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CallAI->InstrnsBefore.push_back( Ad3 );
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CallAI->InstrnsBefore.push_back( Ad4 );
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cerr << "\n Caution: Call arg moved from stack to stack";
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}
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}
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} // for each parameter in call instruction
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// if we added any instruction before the call instruction, verify
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// that they are in the proper order and if not, reorder them
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if( ! AddedInstrnsBefore.empty() ) {
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if( DEBUG_RA) {
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cerr << "\nCalling reorder with instrns: \n";
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for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
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cerr << *(AddedInstrnsBefore[i]);
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}
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vector <MachineInstr *> TmpVec;
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OrderAddedInstrns(AddedInstrnsBefore, TmpVec);
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if( DEBUG_RA) {
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cerr << "\nAfter reordering instrns: \n";
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for(unsigned i=0; i < TmpVec.size(); i++)
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cerr << *(TmpVec[i]);
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}
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// copy the results back from TmpVec to InstrnsBefore
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for(unsigned i=0; i < TmpVec.size(); i++)
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CallAI->InstrnsBefore.push_back( TmpVec[i] );
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}
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// Reset optional args area again to be safe
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//
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PRA.mcInfo.resetOptionalArgs(target);
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@ -1265,3 +1300,201 @@ void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
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cerr << "]" << endl;
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}
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}
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//---------------------------------------------------------------------------
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// This method examines instructions inserted by RegAlloc code before a
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// machine instruction to detect invalid orders that destroy values before
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// they are used. If it detects such conditions, it reorders the instructions.
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//
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// The unordered instructions come in the UnordVec. These instructions are
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// instructions inserted by RegAlloc. All suhc instruction MUST have
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// their USES BEFORE THE DEFS.
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// The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
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// this method is called.
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// This method uses two vectors for efficiency in accessing
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
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vector<MachineInstr *> &OrdVec) const{
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/*
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Problem: We can have instructions inserted by RegAlloc like
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1. add %ox %g0 %oy
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2. add %oy %g0 %oz, where z!=x or z==x
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This is wrong since %oy used by 2 is overwritten by 1
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*/
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/* Algorithm:
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Round 1:
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For each instruction 'Inst' in UnordVec, starting from UnordVec.begin,
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let Def be the destination reg of instr.
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For each use 'Use' of the following instruction
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If Def==Use continue
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If no use is found, push back 'Inst' to OrdVec
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If no inst is left in UnordVec by the end of Round1, return
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Round 2:
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For each inst 'Inst' left in UnordVec
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For each use 'Use' in Inst
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If threre is NO Def for this Use in an inst in OrdVec
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push back Inst
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Else
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push_front a stack save instr mem location "Loc"
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push_back a restore inst to load to Use from Loc
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discard Inst (assert that one operand is %g0)
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*/
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bool CouldMoveAll = true;
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vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
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for( ; DefIt != UnordVec.end(); ++DefIt ) {
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// for each instruction in the UnordVec do ...
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MachineInstr *DefInst = *DefIt;
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// cerr << "\nDefInst = " << *DefInst;
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for(unsigned OpNumD=0; OpNumD < DefInst->getNumOperands(); ++OpNumD) {
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MachineOperand& DefOp = DefInst->getOperand(OpNumD);
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if( DefOp.opIsDef() &&
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DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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// If the operand in DefInst is a def ...
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bool DefEqUse = false;
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vector<MachineInstr *>::iterator UseIt = DefIt;
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UseIt++;
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for( ; UseIt != UnordVec.end(); ++UseIt ) {
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// for each inst (UseInst) that is below the DefInst do ...
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MachineInstr *UseInst = *UseIt;
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for(unsigned OpNumU=0; OpNumU < UseInst->getNumOperands(); ++OpNumU){
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MachineOperand& UseOp = UseInst->getOperand(OpNumU);
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if( ! UseOp.opIsDef() &&
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UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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// if use is a register ...
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if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
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// if Def and this use are the same, it means that this use
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// is destroyed by a def before it is used
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DefEqUse = true;
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CouldMoveAll = false;
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cerr << "\nReordered Ins (Moved up): " << *UseInst;
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break;
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} // if two registers are equal
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} // if use is a register
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} // for all uses
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}// for all use instructions
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if( ! DefEqUse ) {
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// cerr << "\nMoved Inst = " << *DefInst;
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OrdVec.push_back(DefInst);
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*DefIt = NULL;
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}
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else
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break; // exit the loop since we can't move DefInst
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} // if Def is a machine register
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} // for all Defs in DefInst (there should be only 1)
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} // for all instructions in the UnordVec
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if( CouldMoveAll ) {
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assert( (UnordVec.size() == OrdVec.size()) &&
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"Different Vec Sizes after reordering");
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return;
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}
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// We are here because there were two instructions like:
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// 1. add %ox %g0 %oy
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// 2. add %oy %g0 %oz, where z!=x or z==x
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// and hence we could not move 1 to the OrdVec
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// cerr << "\nCaution: Added instructions will be RE-ORDERED !@!@!";
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vector< MachineInstr *>::iterator UnordIt = UnordVec.begin();
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for( ; UnordIt != UnordVec.end(); ++UnordIt ) {
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MachineInstr *UnordInst = *UnordIt;
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if( UnordInst == NULL ) continue;
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for(unsigned OpNumU=0; OpNumU < UnordInst->getNumOperands(); ++OpNumU) {
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MachineOperand& UseOp = UnordInst->getOperand(OpNumU);
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if( ! UseOp.opIsDef() &&
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UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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if( UseOp.getMachineRegNum() == getZeroRegNum() )
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continue;
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// for all uses of UnordInst
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bool DefEqUse = false;
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vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
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for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
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MachineInstr *OrdInst = *OrdIt ;
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for(unsigned OpNumO=0; OpNumO < OrdInst->getNumOperands(); ++OpNumO){
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MachineOperand& DefOp = OrdInst->getOperand(OpNumO);
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if( DefOp.opIsDef() &&
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DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
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DefEqUse = true;
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assert(0 && "Insert save/restre code for reordering");
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} // if two registers are equal
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} // if Def is a register
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} // for all defs
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} // for each instr in OrdVec
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if( !DefEqUse ) {
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OrdVec.push_back( UnordInst );
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cerr << "\nReordered instr (Moved Down): " << *UnordInst;
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}
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} // if the operand in UnordInst is a use
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} // for each use in the UnordInst
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} // for each UnordInst in UnordVec
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}
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