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[X86] Mutate scalar fceil/ffloor/ftrunc/fnearbyint/frint into X86ISD::RNDSCALE during PreProcessIselDAG to cut down on number of isel patterns.

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Similar was done for vectors in r362535. Removes about 1200 bytes from the isel table.

llvm-svn: 362894
This commit is contained in:
Craig Topper 2019-06-08 23:53:31 +00:00
parent 4390ba5b81
commit a4b4a052d7
4 changed files with 23 additions and 121 deletions
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10
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -819,11 +819,8 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
case ISD::FTRUNC:
case ISD::FNEARBYINT:
case ISD::FRINT: {
// Replace vector rounding with their X86 specific equivalent so we don't
// Replace fp rounding with their X86 specific equivalent so we don't
// need 2 sets of patterns.
if (!N->getValueType(0).isVector())
break;
unsigned Imm;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected opcode!");
@ -4709,15 +4706,12 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
case ISD::FTRUNC:
case ISD::FNEARBYINT:
case ISD::FRINT: {
// Replace vector rounding with their X86 specific equivalent so we don't
// Replace fp rounding with their X86 specific equivalent so we don't
// need 2 sets of patterns.
// FIXME: This can only happen when the nodes started as STRICT_* and have
// been mutated into their non-STRICT equivalents. Eventually this
// mutation will be removed and we should switch the STRICT_ nodes to a
// strict version of RNDSCALE in PreProcessISelDAG.
if (!Node->getValueType(0).isVector())
break;
unsigned Imm;
switch (Node->getOpcode()) {
default: llvm_unreachable("Unexpected opcode!");

32
lib/Target/X86/X86InstrAVX512.td
View File

@ -9259,39 +9259,15 @@ multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
}
let Predicates = [HasAVX512] in {
def : Pat<(ffloor _.FRC:$src),
def : Pat<(X86VRndScale _.FRC:$src1, imm:$src2),
(_.EltVT (!cast<Instruction>(NAME##r) (_.EltVT (IMPLICIT_DEF)),
_.FRC:$src, (i32 0x9)))>;
def : Pat<(fceil _.FRC:$src),
(_.EltVT (!cast<Instruction>(NAME##r) (_.EltVT (IMPLICIT_DEF)),
_.FRC:$src, (i32 0xa)))>;
def : Pat<(ftrunc _.FRC:$src),
(_.EltVT (!cast<Instruction>(NAME##r) (_.EltVT (IMPLICIT_DEF)),
_.FRC:$src, (i32 0xb)))>;
def : Pat<(frint _.FRC:$src),
(_.EltVT (!cast<Instruction>(NAME##r) (_.EltVT (IMPLICIT_DEF)),
_.FRC:$src, (i32 0x4)))>;
def : Pat<(fnearbyint _.FRC:$src),
(_.EltVT (!cast<Instruction>(NAME##r) (_.EltVT (IMPLICIT_DEF)),
_.FRC:$src, (i32 0xc)))>;
_.FRC:$src1, imm:$src2))>;
}
let Predicates = [HasAVX512, OptForSize] in {
def : Pat<(ffloor (_.ScalarLdFrag addr:$src)),
def : Pat<(X86VRndScale (_.ScalarLdFrag addr:$src1), imm:$src2),
(_.EltVT (!cast<Instruction>(NAME##m) (_.EltVT (IMPLICIT_DEF)),
addr:$src, (i32 0x9)))>;
def : Pat<(fceil (_.ScalarLdFrag addr:$src)),
(_.EltVT (!cast<Instruction>(NAME##m) (_.EltVT (IMPLICIT_DEF)),
addr:$src, (i32 0xa)))>;
def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)),
(_.EltVT (!cast<Instruction>(NAME##m) (_.EltVT (IMPLICIT_DEF)),
addr:$src, (i32 0xb)))>;
def : Pat<(frint (_.ScalarLdFrag addr:$src)),
(_.EltVT (!cast<Instruction>(NAME##m) (_.EltVT (IMPLICIT_DEF)),
addr:$src, (i32 0x4)))>;
def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)),
(_.EltVT (!cast<Instruction>(NAME##m) (_.EltVT (IMPLICIT_DEF)),
addr:$src, (i32 0xc)))>;
addr:$src1, imm:$src2))>;
}
}

2
lib/Target/X86/X86InstrFragmentsSIMD.td
View File

@ -307,7 +307,7 @@ def SDTFPTernaryOpImm: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisSameAs<0,1>,
SDTCisSameSizeAs<0, 3>,
SDTCisSameNumEltsAs<0, 3>,
SDTCisVT<4, i32>]>;
def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisVec<0>,
def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>,
SDTCisSameAs<0,1>,
SDTCisVT<2, i32>]>;

100
lib/Target/X86/X86InstrSSE.td
View File

@ -5725,51 +5725,17 @@ let Predicates = [UseAVX] in {
}
let Predicates = [UseAVX] in {
def : Pat<(ffloor FR32:$src),
(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
def : Pat<(f32 (fnearbyint FR32:$src)),
(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
def : Pat<(f32 (fceil FR32:$src)),
(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
def : Pat<(f32 (frint FR32:$src)),
(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
def : Pat<(f32 (ftrunc FR32:$src)),
(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
def : Pat<(f64 (ffloor FR64:$src)),
(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
def : Pat<(f64 (fnearbyint FR64:$src)),
(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
def : Pat<(f64 (fceil FR64:$src)),
(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
def : Pat<(f64 (frint FR64:$src)),
(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
def : Pat<(f64 (ftrunc FR64:$src)),
(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
def : Pat<(X86VRndScale FR32:$src1, imm:$src2),
(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src1, imm:$src2)>;
def : Pat<(X86VRndScale FR64:$src1, imm:$src2),
(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src1, imm:$src2)>;
}
let Predicates = [UseAVX, OptForSize] in {
def : Pat<(ffloor (loadf32 addr:$src)),
(VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0x9))>;
def : Pat<(f32 (fnearbyint (loadf32 addr:$src))),
(VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xC))>;
def : Pat<(f32 (fceil (loadf32 addr:$src))),
(VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xA))>;
def : Pat<(f32 (frint (loadf32 addr:$src))),
(VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0x4))>;
def : Pat<(f32 (ftrunc (loadf32 addr:$src))),
(VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xB))>;
def : Pat<(f64 (ffloor (loadf64 addr:$src))),
(VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0x9))>;
def : Pat<(f64 (fnearbyint (loadf64 addr:$src))),
(VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xC))>;
def : Pat<(f64 (fceil (loadf64 addr:$src))),
(VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xA))>;
def : Pat<(f64 (frint (loadf64 addr:$src))),
(VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0x4))>;
def : Pat<(f64 (ftrunc (loadf64 addr:$src))),
(VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xB))>;
def : Pat<(X86VRndScale (loadf32 addr:$src1), imm:$src2),
(VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src1, imm:$src2)>;
def : Pat<(X86VRndScale (loadf64 addr:$src1), imm:$src2),
(VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src1, imm:$src2)>;
}
let ExeDomain = SSEPackedSingle in
@ -5786,51 +5752,17 @@ defm ROUND : sse41_fp_binop_s<0x0A, 0x0B, "round", SchedWriteFRnd.Scl,
v4f32, v2f64, X86RndScales>;
let Predicates = [UseSSE41] in {
def : Pat<(ffloor FR32:$src),
(ROUNDSSr FR32:$src, (i32 0x9))>;
def : Pat<(f32 (fnearbyint FR32:$src)),
(ROUNDSSr FR32:$src, (i32 0xC))>;
def : Pat<(f32 (fceil FR32:$src)),
(ROUNDSSr FR32:$src, (i32 0xA))>;
def : Pat<(f32 (frint FR32:$src)),
(ROUNDSSr FR32:$src, (i32 0x4))>;
def : Pat<(f32 (ftrunc FR32:$src)),
(ROUNDSSr FR32:$src, (i32 0xB))>;
def : Pat<(f64 (ffloor FR64:$src)),
(ROUNDSDr FR64:$src, (i32 0x9))>;
def : Pat<(f64 (fnearbyint FR64:$src)),
(ROUNDSDr FR64:$src, (i32 0xC))>;
def : Pat<(f64 (fceil FR64:$src)),
(ROUNDSDr FR64:$src, (i32 0xA))>;
def : Pat<(f64 (frint FR64:$src)),
(ROUNDSDr FR64:$src, (i32 0x4))>;
def : Pat<(f64 (ftrunc FR64:$src)),
(ROUNDSDr FR64:$src, (i32 0xB))>;
def : Pat<(X86VRndScale FR32:$src1, imm:$src2),
(ROUNDSSr FR32:$src1, imm:$src2)>;
def : Pat<(X86VRndScale FR64:$src1, imm:$src2),
(ROUNDSDr FR64:$src1, imm:$src2)>;
}
let Predicates = [UseSSE41, OptForSize] in {
def : Pat<(ffloor (loadf32 addr:$src)),
(ROUNDSSm addr:$src, (i32 0x9))>;
def : Pat<(f32 (fnearbyint (loadf32 addr:$src))),
(ROUNDSSm addr:$src, (i32 0xC))>;
def : Pat<(f32 (fceil (loadf32 addr:$src))),
(ROUNDSSm addr:$src, (i32 0xA))>;
def : Pat<(f32 (frint (loadf32 addr:$src))),
(ROUNDSSm addr:$src, (i32 0x4))>;
def : Pat<(f32 (ftrunc (loadf32 addr:$src))),
(ROUNDSSm addr:$src, (i32 0xB))>;
def : Pat<(f64 (ffloor (loadf64 addr:$src))),
(ROUNDSDm addr:$src, (i32 0x9))>;
def : Pat<(f64 (fnearbyint (loadf64 addr:$src))),
(ROUNDSDm addr:$src, (i32 0xC))>;
def : Pat<(f64 (fceil (loadf64 addr:$src))),
(ROUNDSDm addr:$src, (i32 0xA))>;
def : Pat<(f64 (frint (loadf64 addr:$src))),
(ROUNDSDm addr:$src, (i32 0x4))>;
def : Pat<(f64 (ftrunc (loadf64 addr:$src))),
(ROUNDSDm addr:$src, (i32 0xB))>;
def : Pat<(X86VRndScale (loadf32 addr:$src1), imm:$src2),
(ROUNDSSm addr:$src1, imm:$src2)>;
def : Pat<(X86VRndScale (loadf64 addr:$src1), imm:$src2),
(ROUNDSDm addr:$src1, imm:$src2)>;
}
//===----------------------------------------------------------------------===//