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[mips] Support sigrie instruction

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The `sigrie` instruction signals a Reserved Instruction Exception.
This patch adds support for assembling / disassembling the instruction.

Differential Revision: http://reviews.llvm.org/D53861

llvm-svn: 346230
This commit is contained in:
Simon Atanasyan 2018-11-06 14:37:24 +00:00
parent 9307155a7b
commit a4f6821812
9 changed files with 59 additions and 1 deletions
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11
lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -159,6 +159,7 @@ class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
@ -1162,6 +1163,14 @@ class SDBBP_MMR6_DESC : MipsR6Inst {
InstrItinClass Itinerary = II_SDBBP;
}
class SIGRIE_MMR6_DESC : MipsR6Inst {
dag OutOperandList = (outs);
dag InOperandList = (ins uimm16:$code_);
string AsmString = !strconcat("sigrie", "\t$code_");
list<dag> Pattern = [];
InstrItinClass Itinerary = II_SIGRIE;
}
class LWM16_MMR6_DESC
: MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
!strconcat("lwm16", "\t$rt, $addr"), [],
@ -1427,6 +1436,7 @@ def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
ISA_MICROMIPS32R6;
def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC, ISA_MICROMIPS32R6;
def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
let DecoderMethod = "DecodeMemMMImm16" in {
@ -1635,6 +1645,7 @@ def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
}
def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"sigrie", (SIGRIE_MMR6 0), 1>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"rdhwr $rt, $rs",
(RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
ISA_MICROMIPS32R6;

11
lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -933,6 +933,17 @@ class SDBBP_FM_MM : MMArch {
let Inst{5-0} = 0x3c;
}
class SIGRIE_FM_MM : MMArch {
bits<16> code_;
bits<32> Inst;
let Inst{31-26} = 0x0;
let Inst{25-22} = 0x0;
let Inst{21-6} = code_;
let Inst{5-0} = 0b111111;
}
class RDHWR_FM_MM : MMArch {
bits<5> rt;
bits<5> rd;

10
lib/Target/Mips/Mips32r6InstrFormats.td
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@ -87,6 +87,7 @@ def OPCODE5_BC1NEZ : OPCODE5<0b01101>;
def OPCODE5_BC2EQZ : OPCODE5<0b01001>;
def OPCODE5_BC2NEZ : OPCODE5<0b01101>;
def OPCODE5_BGEZAL : OPCODE5<0b10001>;
def OPCODE5_SIGRIE : OPCODE5<0b10111>;
// The next four constants are unnamed in the spec. These names are taken from
// the OPGROUP names they are used with.
def OPCODE5_LDC2 : OPCODE5<0b01110>;
@ -602,3 +603,12 @@ class SPECIAL3_GINV<bits<2> ginv> : MipsR6Inst {
let Inst{7-6} = ginv;
let Inst{5-0} = 0b111101;
}
class SIGRIE_FM : MipsR6Inst {
bits<16> code_;
let Inst{31-26} = OPGROUP_REGIMM.Value;
let Inst{25-21} = 0;
let Inst{20-16} = OPCODE5_SIGRIE.Value;
let Inst{15-0} = code_;
}

12
lib/Target/Mips/Mips32r6InstrInfo.td
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@ -200,6 +200,8 @@ class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;
class GINVI_ENC : SPECIAL3_GINV<0>;
class GINVT_ENC : SPECIAL3_GINV<2>;
class SIGRIE_ENC : SIGRIE_FM;
//===----------------------------------------------------------------------===//
//
// Instruction Multiclasses
@ -846,6 +848,14 @@ class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
}
class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
class SIGRIE_DESC {
dag OutOperandList = (outs);
dag InOperandList = (ins uimm16:$code_);
string AsmString = "sigrie\t$code_";
list<dag> Pattern = [];
InstrItinClass Itinerary = II_SIGRIE;
}
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@ -961,6 +971,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
}
let AdditionalPredicates = [NotInMicroMips] in {
@ -988,6 +999,7 @@ def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
}

2
lib/Target/Mips/MipsSchedule.td
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@ -154,6 +154,7 @@ def II_DERET : InstrItinClass;
def II_ERETNC : InstrItinClass;
def II_EHB : InstrItinClass;
def II_SDBBP : InstrItinClass;
def II_SIGRIE : InstrItinClass;
def II_SSNOP : InstrItinClass;
def II_SYSCALL : InstrItinClass;
def II_PAUSE : InstrItinClass;
@ -546,6 +547,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_ERETNC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_EHB , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SDBBP , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SIGRIE , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SSNOP , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SYSCALL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,

2
lib/Target/Mips/MipsScheduleGeneric.td
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@ -179,7 +179,7 @@ def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>;
def : ItinRW<[GenericWriteTrap], [II_BREAK, II_SYSCALL, II_TEQ, II_TEQI,
II_TGE, II_TGEI, II_TGEIU, II_TGEU, II_TNE,
II_TNEI, II_TLT, II_TLTI, II_TLTU, II_TTLTIU,
II_TRAP, II_SDBBP]>;
II_TRAP, II_SDBBP, II_SIGRIE]>;
// COP0 Pipeline
// =============

4
test/MC/Mips/micromips32r6/valid.s
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@ -169,6 +169,10 @@
rdpgpr $3, $9 # CHECK: $3, $9 # encoding: [0x00,0x69,0xe1,0x7c]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
sigrie # CHECK: sigrie # encoding: [0x00,0x00,0x00,0x3f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE_MM
sigrie 257 # CHECK: sigrie 257 # encoding: [0x00,0x00,0x40,0x7f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE_MM
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]

4
test/MC/Mips/mips32r6/valid.s
View File

@ -281,6 +281,10 @@ a:
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sigrie # CHECK: sigrie # encoding: [0x04,0x17,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
sigrie 257 # CHECK: sigrie 257 # encoding: [0x04,0x17,0x01,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]

4
test/MC/Mips/mips64r6/valid.s
View File

@ -242,6 +242,10 @@ a:
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sigrie # CHECK: sigrie # encoding: [0x04,0x17,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
sigrie 257 # CHECK: sigrie 257 # encoding: [0x04,0x17,0x01,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]