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R600/SI: rework VOP3 classes

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Order the classes and add asm operands.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175751
This commit is contained in:
Christian Konig 2013-02-21 15:17:09 +00:00
parent 049fe6c2a3
commit a544d6c0b9
1 changed files with 14 additions and 14 deletions
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28
lib/Target/R600/SIInstrInfo.td
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@ -127,20 +127,6 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
// Vector ALU classes
//===----------------------------------------------------------------------===//
class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_32:$dst),
(ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3,
i32imm:$src4, i32imm:$src5, i32imm:$src6),
opName, pattern
>;
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_64:$dst),
(ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2,
i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
opName, pattern
>;
multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
string opName, list<dag> pattern> {
@ -224,6 +210,20 @@ multiclass VOPC_64 <bits<8> op, string opName,
ValueType vt = untyped, PatLeaf cond = COND_NULL>
: VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>;
class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_32:$dst),
(ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2,
i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
>;
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_64:$dst),
(ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2,
i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
>;
//===----------------------------------------------------------------------===//
// Vector I/O classes
//===----------------------------------------------------------------------===//