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[ARM] Introduce subtarget features per ARM architecture.
This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
This commit is contained in:
Bradley Smith
parent
2381ae757a
commit
a56404a4e7
@ -86,8 +86,9 @@ protected:
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void InitMCProcessorInfo(StringRef CPU, StringRef FS);
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public:
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/// Set the features to the default for the given CPU.
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void setDefaultFeatures(StringRef CPU);
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/// Set the features to the default for the given CPU with an appended feature
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/// string.
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void setDefaultFeatures(StringRef CPU, StringRef FS);
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version does not change the implied bits.
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@ -32,8 +32,8 @@ void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
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CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
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}
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void MCSubtargetInfo::setDefaultFeatures(StringRef CPU) {
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FeatureBits = getFeatures(CPU, "", ProcDesc, ProcFeatures);
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void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
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FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
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}
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MCSubtargetInfo::MCSubtargetInfo(
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@ -16,6 +16,17 @@
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Helper classes.
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//
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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class Architecture<string fname, string aname, list<SubtargetFeature> features >
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: SubtargetFeature<fname, "ARMArch", aname,
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!strconcat(aname, " architecture"), features>;
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//===----------------------------------------------------------------------===//
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// ARM Subtarget state.
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//
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@ -52,7 +63,7 @@ def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
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"true", "Enable ARMv8 FP",
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[FeatureVFP4]>;
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def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
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"Restrict VFP3 to 16 double registers">;
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"Restrict FP to 16 double registers">;
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def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
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"Enable divide instructions">;
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def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
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@ -167,7 +178,11 @@ def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
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"Don't use movt/movw pairs for 32-bit "
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"imms">;
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// ARM ISAs.
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//===----------------------------------------------------------------------===//
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// ARM ISAa.
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//
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def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
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"Support ARM v4T instructions">;
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def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
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@ -193,296 +208,419 @@ def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
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[HasV6T2Ops, FeaturePerfMon]>;
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def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
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"Support ARM v8 instructions",
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[HasV7Ops, FeatureVirtualization,
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FeatureMP]>;
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[HasV7Ops]>;
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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"Support ARM v8.1a instructions",
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[HasV8Ops, FeatureAClass, FeatureCRC]>;
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[HasV8Ops]>;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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// ARM Processor subtarget features.
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//
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def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
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"Cortex-A5 ARM processors", []>;
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def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
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"Cortex-A7 ARM processors", []>;
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def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
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"Cortex-A8 ARM processors", []>;
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def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
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"Cortex-A9 ARM processors", []>;
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def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
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"Cortex-A12 ARM processors", []>;
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def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
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"Cortex-A15 ARM processors", []>;
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def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
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"Cortex-A17 ARM processors", []>;
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors", []>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors", []>;
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def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
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"Cortex-A72 ARM processors", []>;
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def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
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"Qualcomm ARM processors", []>;
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def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
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"Swift ARM processors", []>;
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def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
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"Cortex-R4 ARM processors", []>;
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def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
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"Cortex-R5 ARM processors", []>;
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def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
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"Cortex-R7 ARM processors", []>;
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//===----------------------------------------------------------------------===//
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// ARM schedules.
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//
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include "ARMSchedule.td"
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// ARM processor families.
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def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
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"Cortex-A5 ARM processors",
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[FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding, FeatureT2XtPk,
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FeatureTrustZone, FeatureMP]>;
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def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
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"Cortex-A7 ARM processors",
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[FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding, FeatureT2XtPk,
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FeatureVFP4, FeatureMP,
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FeatureHWDiv, FeatureHWDivARM,
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FeatureTrustZone, FeatureVirtualization]>;
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def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
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"Cortex-A8 ARM processors",
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[FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding, FeatureT2XtPk,
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FeatureTrustZone]>;
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def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
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"Cortex-A9 ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeatureTrustZone]>;
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def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
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"Swift ARM processors",
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[FeatureNEONForFP, FeatureT2XtPk,
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FeatureVFP4, FeatureMP, FeatureHWDiv,
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FeatureHWDivARM, FeatureAvoidPartialCPSR,
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FeatureAvoidMOVsShOp,
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FeatureHasSlowFPVMLx, FeatureTrustZone]>;
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def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
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"Cortex-A12 ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureVFP4,
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FeatureHWDiv, FeatureHWDivARM,
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FeatureAvoidPartialCPSR,
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FeatureVirtualization,
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FeatureTrustZone]>;
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//===----------------------------------------------------------------------===//
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// ARM architectures
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//
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// FIXME: It has not been determined if A15 has these features.
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def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
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"Cortex-A15 ARM processors",
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[FeatureT2XtPk, FeatureVFP4,
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FeatureMP, FeatureHWDiv, FeatureHWDivARM,
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FeatureAvoidPartialCPSR,
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FeatureTrustZone, FeatureVirtualization]>;
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def ARMv2 : Architecture<"armv2", "ARMv2", []>;
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def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
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"Cortex-A17 ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureVFP4,
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FeatureHWDiv, FeatureHWDivARM,
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FeatureAvoidPartialCPSR,
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FeatureVirtualization,
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FeatureTrustZone]>;
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def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors",
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[FeatureHWDiv, FeatureHWDivARM,
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FeatureTrustZone, FeatureT2XtPk,
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FeatureCrypto, FeatureCRC]>;
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def ARMv3 : Architecture<"armv3", "ARMv3", []>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors",
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[FeatureHWDiv, FeatureHWDivARM,
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FeatureTrustZone, FeatureT2XtPk,
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FeatureCrypto, FeatureCRC]>;
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def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
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def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
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"Cortex-R4 ARM processors",
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[FeatureHWDiv,
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FeatureAvoidPartialCPSR,
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FeatureDSP, FeatureT2XtPk, HasV7Ops,
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FeatureDB, FeatureHasRAS, FeatureRClass]>;
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def ARMv4 : Architecture<"armv4", "ARMv4", []>;
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def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
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"Cortex-R5 ARM processors",
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[FeatureSlowFPBrcc,
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FeatureHWDiv, FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureAvoidPartialCPSR,
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FeatureT2XtPk]>;
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def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
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// FIXME: krait has currently the same features as A9
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// plus VFP4 and hardware division features.
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def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
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"Qualcomm ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeatureTrustZone,
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FeatureVFP4,
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FeatureHWDiv,
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FeatureHWDivARM]>;
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def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
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def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
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// V4 Processors.
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def : ProcNoItin<"generic", []>;
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def : ProcNoItin<"arm8", []>;
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def : ProcNoItin<"arm810", []>;
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def : ProcNoItin<"strongarm", []>;
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def : ProcNoItin<"strongarm110", []>;
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def : ProcNoItin<"strongarm1100", []>;
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def : ProcNoItin<"strongarm1110", []>;
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def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
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// V4T Processors.
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def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
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def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
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def : ProcNoItin<"arm710t", [HasV4TOps]>;
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def : ProcNoItin<"arm720t", [HasV4TOps]>;
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def : ProcNoItin<"arm9", [HasV4TOps]>;
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def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
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def : ProcNoItin<"arm920", [HasV4TOps]>;
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def : ProcNoItin<"arm920t", [HasV4TOps]>;
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def : ProcNoItin<"arm922t", [HasV4TOps]>;
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def : ProcNoItin<"arm940t", [HasV4TOps]>;
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def : ProcNoItin<"ep9312", [HasV4TOps]>;
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// V5T Processors.
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def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
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def : ProcNoItin<"arm1020t", [HasV5TOps]>;
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// V5TE Processors.
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def : ProcNoItin<"arm9e", [HasV5TEOps]>;
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def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm10e", [HasV5TEOps]>;
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def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
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def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
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def : ProcNoItin<"xscale", [HasV5TEOps]>;
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def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
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// V6 Processors.
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def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
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def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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// V6M Processors.
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def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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def : Processor<"cortex-m0plus", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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def : Processor<"cortex-m1", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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def : Processor<"sc000", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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// V6K Processors.
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def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6KOps,
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FeatureTrustZone]>;
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def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
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FeatureTrustZone,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6KOps]>;
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def : Processor<"mpcore", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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// V6T2 Processors.
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def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, FeatureDSP]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx,
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def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
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FeatureDSP]>;
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// V7a Processors.
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def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
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def ARMv6z : Architecture<"armv6z", "ARMv6z", [HasV6KOps,
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FeatureTrustZone]>;
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def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
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FeatureNoARM,
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FeatureDB,
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FeatureMClass]>;
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def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
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FeatureNoARM,
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FeatureDB,
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FeatureMClass]>;
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def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
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FeatureNEON,
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FeatureDB,
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FeatureDSP,
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FeatureAClass]>;
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def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
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FeatureDB,
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FeatureDSP,
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FeatureHWDiv,
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FeatureRClass]>;
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def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
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FeatureThumb2,
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FeatureNoARM,
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FeatureDB,
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FeatureHWDiv,
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FeatureMClass]>;
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def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
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FeatureThumb2,
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FeatureNoARM,
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FeatureDB,
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FeatureHWDiv,
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FeatureMClass,
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FeatureDSP,
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FeatureT2XtPk]>;
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def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
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FeatureAClass,
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FeatureDB,
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FeatureFPARMv8,
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FeatureNEON,
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FeatureDSP,
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FeatureTrustZone,
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FeatureMP,
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FeatureVirtualization,
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FeatureCrypto,
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FeatureCRC]>;
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def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
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FeatureAClass,
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FeatureDB,
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FeatureFPARMv8,
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FeatureNEON,
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FeatureDSP,
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FeatureTrustZone,
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FeatureMP,
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FeatureVirtualization,
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FeatureCrypto,
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FeatureCRC]>;
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// Aliases
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def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
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def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
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def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
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def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
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def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
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def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
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//===----------------------------------------------------------------------===//
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// ARM processors
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//
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// Dummy CPU, used to target architectures
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def : ProcNoItin<"generic", []>;
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def : ProcNoItin<"arm8", [ARMv4]>;
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def : ProcNoItin<"arm810", [ARMv4]>;
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def : ProcNoItin<"strongarm", [ARMv4]>;
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def : ProcNoItin<"strongarm110", [ARMv4]>;
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def : ProcNoItin<"strongarm1100", [ARMv4]>;
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def : ProcNoItin<"strongarm1110", [ARMv4]>;
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def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
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def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
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||||
def : ProcNoItin<"arm710t", [ARMv4t]>;
|
||||
def : ProcNoItin<"arm720t", [ARMv4t]>;
|
||||
def : ProcNoItin<"arm9", [ARMv4t]>;
|
||||
def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
|
||||
def : ProcNoItin<"arm920", [ARMv4t]>;
|
||||
def : ProcNoItin<"arm920t", [ARMv4t]>;
|
||||
def : ProcNoItin<"arm922t", [ARMv4t]>;
|
||||
def : ProcNoItin<"arm940t", [ARMv4t]>;
|
||||
def : ProcNoItin<"ep9312", [ARMv4t]>;
|
||||
|
||||
def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
|
||||
def : ProcNoItin<"arm1020t", [ARMv5t]>;
|
||||
|
||||
def : ProcNoItin<"arm9e", [ARMv5te]>;
|
||||
def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
|
||||
def : ProcNoItin<"arm946e-s", [ARMv5te]>;
|
||||
def : ProcNoItin<"arm966e-s", [ARMv5te]>;
|
||||
def : ProcNoItin<"arm968e-s", [ARMv5te]>;
|
||||
def : ProcNoItin<"arm10e", [ARMv5te]>;
|
||||
def : ProcNoItin<"arm1020e", [ARMv5te]>;
|
||||
def : ProcNoItin<"arm1022e", [ARMv5te]>;
|
||||
def : ProcNoItin<"xscale", [ARMv5te]>;
|
||||
def : ProcNoItin<"iwmmxt", [ARMv5te]>;
|
||||
|
||||
def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
|
||||
def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
|
||||
FeatureVFP2,
|
||||
FeatureHasSlowFPVMLx]>;
|
||||
|
||||
def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
|
||||
def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
|
||||
def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
|
||||
def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
|
||||
|
||||
def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6z]>;
|
||||
def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6z,
|
||||
FeatureVFP2,
|
||||
FeatureHasSlowFPVMLx]>;
|
||||
|
||||
def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
|
||||
def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
|
||||
FeatureVFP2,
|
||||
FeatureHasSlowFPVMLx]>;
|
||||
|
||||
def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
|
||||
def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
|
||||
FeatureVFP2,
|
||||
FeatureHasSlowFPVMLx]>;
|
||||
|
||||
// FIXME: A5 has currently the same Schedule model as A8
|
||||
def : ProcessorModel<"cortex-a5", CortexA8Model,
|
||||
[ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
|
||||
FeatureVFP4, FeatureDSP,
|
||||
FeatureHasRAS, FeatureAClass]>;
|
||||
def : ProcessorModel<"cortex-a7", CortexA8Model,
|
||||
[ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
|
||||
FeatureDSP, FeatureHasRAS, FeatureAClass]>;
|
||||
def : ProcessorModel<"cortex-a8", CortexA8Model,
|
||||
[ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
|
||||
FeatureDSP, FeatureHasRAS, FeatureAClass]>;
|
||||
def : ProcessorModel<"cortex-a9", CortexA9Model,
|
||||
[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
|
||||
FeatureDSP, FeatureHasRAS, FeatureMP,
|
||||
FeatureAClass]>;
|
||||
def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
|
||||
FeatureHasRAS,
|
||||
FeatureTrustZone,
|
||||
FeatureSlowFPBrcc,
|
||||
FeatureHasSlowFPVMLx,
|
||||
FeatureVMLxForwarding,
|
||||
FeatureT2XtPk,
|
||||
FeatureMP,
|
||||
FeatureVFP4]>;
|
||||
|
||||
def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
|
||||
FeatureHasRAS,
|
||||
FeatureTrustZone,
|
||||
FeatureSlowFPBrcc,
|
||||
FeatureHasSlowFPVMLx,
|
||||
FeatureVMLxForwarding,
|
||||
FeatureT2XtPk,
|
||||
FeatureMP,
|
||||
FeatureVFP4,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureVirtualization]>;
|
||||
|
||||
def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
|
||||
FeatureHasRAS,
|
||||
FeatureTrustZone,
|
||||
FeatureSlowFPBrcc,
|
||||
FeatureHasSlowFPVMLx,
|
||||
FeatureVMLxForwarding,
|
||||
FeatureT2XtPk]>;
|
||||
|
||||
def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
|
||||
FeatureHasRAS,
|
||||
FeatureTrustZone,
|
||||
FeatureVMLxForwarding,
|
||||
FeatureT2XtPk,
|
||||
FeatureFP16,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureMP]>;
|
||||
|
||||
// FIXME: A12 has currently the same Schedule model as A9
|
||||
def : ProcessorModel<"cortex-a12", CortexA9Model,
|
||||
[ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
|
||||
FeatureDSP, FeatureMP,
|
||||
FeatureHasRAS, FeatureAClass]>;
|
||||
def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
|
||||
FeatureHasRAS,
|
||||
FeatureTrustZone,
|
||||
FeatureVMLxForwarding,
|
||||
FeatureT2XtPk,
|
||||
FeatureVFP4,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureVirtualization,
|
||||
FeatureMP]>;
|
||||
|
||||
// FIXME: A15 has currently the same ProcessorModel as A9.
|
||||
def : ProcessorModel<"cortex-a15", CortexA9Model,
|
||||
[ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
|
||||
FeatureDSP, FeatureHasRAS, FeatureAClass]>;
|
||||
// FIXME: A15 has currently the same Schedule model as A9.
|
||||
def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
|
||||
FeatureHasRAS,
|
||||
FeatureTrustZone,
|
||||
FeatureT2XtPk,
|
||||
FeatureVFP4,
|
||||
FeatureMP,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureVirtualization]>;
|
||||
|
||||
// FIXME: A17 has currently the same Schedule model as A9
|
||||
def : ProcessorModel<"cortex-a17", CortexA9Model,
|
||||
[ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
|
||||
FeatureDSP, FeatureMP,
|
||||
FeatureHasRAS, FeatureAClass]>;
|
||||
def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
|
||||
FeatureHasRAS,
|
||||
FeatureTrustZone,
|
||||
FeatureMP,
|
||||
FeatureVMLxForwarding,
|
||||
FeatureT2XtPk,
|
||||
FeatureVFP4,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureVirtualization]>;
|
||||
|
||||
// FIXME: krait has currently the same Schedule model as A9
|
||||
def : ProcessorModel<"krait", CortexA9Model,
|
||||
[ProcKrait, HasV7Ops,
|
||||
FeatureNEON, FeatureDB,
|
||||
FeatureDSP, FeatureHasRAS, FeatureAClass]>;
|
||||
// FIXME: krait has currently the same features as A9 plus VFP4 and hardware
|
||||
// division features.
|
||||
def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
|
||||
FeatureHasRAS,
|
||||
FeatureVMLxForwarding,
|
||||
FeatureT2XtPk,
|
||||
FeatureFP16,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureVFP4,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM]>;
|
||||
|
||||
def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
|
||||
FeatureHasRAS,
|
||||
FeatureNEONForFP,
|
||||
FeatureT2XtPk,
|
||||
FeatureVFP4,
|
||||
FeatureMP,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureAvoidMOVsShOp,
|
||||
FeatureHasSlowFPVMLx]>;
|
||||
|
||||
// FIXME: R4 has currently the same ProcessorModel as A8.
|
||||
def : ProcessorModel<"cortex-r4", CortexA8Model,
|
||||
[ProcR4]>;
|
||||
def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
|
||||
FeatureHasRAS,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureT2XtPk]>;
|
||||
|
||||
// FIXME: R4F has currently the same ProcessorModel as A8.
|
||||
def : ProcessorModel<"cortex-r4f", CortexA8Model,
|
||||
[ProcR4,
|
||||
FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
|
||||
FeatureVFP3, FeatureD16]>;
|
||||
def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
|
||||
FeatureHasRAS,
|
||||
FeatureSlowFPBrcc,
|
||||
FeatureHasSlowFPVMLx,
|
||||
FeatureVFP3,
|
||||
FeatureD16,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureT2XtPk]>;
|
||||
|
||||
// FIXME: R5 has currently the same ProcessorModel as A8.
|
||||
def : ProcessorModel<"cortex-r5", CortexA8Model,
|
||||
[ProcR5, HasV7Ops, FeatureDB,
|
||||
FeatureVFP3, FeatureDSP, FeatureHasRAS,
|
||||
FeatureD16, FeatureRClass]>;
|
||||
def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
|
||||
FeatureHasRAS,
|
||||
FeatureVFP3,
|
||||
FeatureD16,
|
||||
FeatureSlowFPBrcc,
|
||||
FeatureHWDivARM,
|
||||
FeatureHasSlowFPVMLx,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureT2XtPk]>;
|
||||
|
||||
// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
|
||||
def : ProcessorModel<"cortex-r7", CortexA8Model,
|
||||
[ProcR5, HasV7Ops, FeatureDB,
|
||||
FeatureVFP3, FeatureDSP,
|
||||
FeatureHasRAS, FeatureVFPOnlySP,
|
||||
FeatureD16, FeatureMP, FeatureRClass]>;
|
||||
def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
|
||||
FeatureHasRAS,
|
||||
FeatureVFP3,
|
||||
FeatureVFPOnlySP,
|
||||
FeatureD16,
|
||||
FeatureMP,
|
||||
FeatureSlowFPBrcc,
|
||||
FeatureHWDivARM,
|
||||
FeatureHasSlowFPVMLx,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureT2XtPk]>;
|
||||
|
||||
// V7M Processors.
|
||||
def : ProcNoItin<"cortex-m3", [HasV7Ops,
|
||||
FeatureThumb2, FeatureNoARM, FeatureDB,
|
||||
FeatureHWDiv, FeatureMClass]>;
|
||||
def : ProcNoItin<"sc300", [HasV7Ops,
|
||||
FeatureThumb2, FeatureNoARM, FeatureDB,
|
||||
FeatureHWDiv, FeatureMClass]>;
|
||||
def : ProcNoItin<"cortex-m3", [ARMv7m]>;
|
||||
def : ProcNoItin<"sc300", [ARMv7m]>;
|
||||
|
||||
// V7EM Processors.
|
||||
def : ProcNoItin<"cortex-m4", [HasV7Ops,
|
||||
FeatureThumb2, FeatureNoARM, FeatureDB,
|
||||
FeatureHWDiv, FeatureDSP, FeatureT2XtPk,
|
||||
FeatureVFP4, FeatureVFPOnlySP, FeatureD16,
|
||||
FeatureMClass]>;
|
||||
def : ProcNoItin<"cortex-m7", [HasV7Ops,
|
||||
FeatureThumb2, FeatureNoARM, FeatureDB,
|
||||
FeatureHWDiv, FeatureDSP,
|
||||
FeatureT2XtPk, FeatureFPARMv8,
|
||||
FeatureD16, FeatureMClass]>;
|
||||
def : ProcNoItin<"cortex-m4", [ARMv7em,
|
||||
FeatureVFP4,
|
||||
FeatureVFPOnlySP,
|
||||
FeatureD16]>;
|
||||
|
||||
def : ProcNoItin<"cortex-m7", [ARMv7em,
|
||||
FeatureFPARMv8,
|
||||
FeatureD16]>;
|
||||
|
||||
|
||||
// Swift uArch Processors.
|
||||
def : ProcessorModel<"swift", SwiftModel,
|
||||
[ProcSwift, HasV7Ops, FeatureNEON,
|
||||
FeatureDB, FeatureDSP,
|
||||
FeatureHasRAS, FeatureAClass]>;
|
||||
def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureT2XtPk,
|
||||
FeatureCrypto,
|
||||
FeatureCRC]>;
|
||||
|
||||
// V8 Processors
|
||||
def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
|
||||
FeatureDB, FeatureFPARMv8,
|
||||
FeatureNEON, FeatureDSP]>;
|
||||
def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
|
||||
FeatureDB, FeatureFPARMv8,
|
||||
FeatureNEON, FeatureDSP]>;
|
||||
// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
|
||||
def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass,
|
||||
FeatureDB, FeatureFPARMv8,
|
||||
FeatureNEON, FeatureDSP]>;
|
||||
def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureT2XtPk,
|
||||
FeatureCrypto,
|
||||
FeatureCRC]>;
|
||||
|
||||
def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureT2XtPk,
|
||||
FeatureCrypto,
|
||||
FeatureCRC]>;
|
||||
|
||||
// Cyclone is very similar to swift
|
||||
def : ProcessorModel<"cyclone", SwiftModel,
|
||||
[ProcSwift, HasV8Ops, HasV7Ops,
|
||||
FeatureCrypto, FeatureFPARMv8,
|
||||
FeatureDB, FeatureDSP,
|
||||
FeatureHasRAS, FeatureZCZeroing]>;
|
||||
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
|
||||
FeatureHasRAS,
|
||||
FeatureNEONForFP,
|
||||
FeatureT2XtPk,
|
||||
FeatureVFP4,
|
||||
FeatureMP,
|
||||
FeatureHWDiv,
|
||||
FeatureHWDivARM,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureAvoidMOVsShOp,
|
||||
FeatureHasSlowFPVMLx,
|
||||
FeatureCrypto,
|
||||
FeatureZCZeroing]>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register File Description
|
||||
|
||||
@ -43,11 +43,17 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
|
||||
protected:
|
||||
enum ARMProcFamilyEnum {
|
||||
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
|
||||
CortexA17, CortexR4, CortexR4F, CortexR5, Swift, CortexA53, CortexA57, Krait,
|
||||
CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexA53, CortexA57,
|
||||
CortexA72, Krait, Swift
|
||||
};
|
||||
enum ARMProcClassEnum {
|
||||
None, AClass, RClass, MClass
|
||||
};
|
||||
enum ARMArchEnum {
|
||||
ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
|
||||
ARMv5tej, ARMv6, ARMv6k, ARMv6z, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
|
||||
ARMv7m, ARMv7em, ARMv8a, ARMv81a
|
||||
};
|
||||
|
||||
/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
|
||||
ARMProcFamilyEnum ARMProcFamily;
|
||||
@ -55,6 +61,9 @@ protected:
|
||||
/// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
|
||||
ARMProcClassEnum ARMProcClass;
|
||||
|
||||
/// ARMArch - ARM architecture
|
||||
ARMArchEnum ARMArch;
|
||||
|
||||
/// HasV4TOps, HasV5TOps, HasV5TEOps,
|
||||
/// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
|
||||
/// Specify whether target support specific ARM ISA variants.
|
||||
|
||||
@ -9040,7 +9040,7 @@ bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
|
||||
|
||||
Triple T;
|
||||
MCSubtargetInfo &STI = copySTI();
|
||||
STI.setDefaultFeatures(T.getARMCPUForArch(Arch));
|
||||
STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
|
||||
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
|
||||
|
||||
getTargetStreamer().emitArch(ID);
|
||||
@ -9173,7 +9173,7 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
|
||||
}
|
||||
|
||||
MCSubtargetInfo &STI = copySTI();
|
||||
STI.setDefaultFeatures(CPU);
|
||||
STI.setDefaultFeatures(CPU, "");
|
||||
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
|
||||
|
||||
return false;
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#include "llvm/MC/MCStreamer.h"
|
||||
#include "llvm/MC/MCSubtargetInfo.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/TargetParser.h"
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
|
||||
using namespace llvm;
|
||||
@ -134,110 +135,11 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
|
||||
bool isThumb =
|
||||
TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
|
||||
|
||||
bool NoCPU = CPU == "generic" || CPU.empty();
|
||||
std::string ARMArchFeature;
|
||||
switch (TT.getSubArch()) {
|
||||
default:
|
||||
llvm_unreachable("invalid sub-architecture for ARM");
|
||||
case Triple::ARMSubArch_v8:
|
||||
if (NoCPU)
|
||||
// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP,
|
||||
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
|
||||
// FeatureT2XtPk, FeatureCrypto, FeatureCRC
|
||||
ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+dsp,+mp,+hwdiv,+hwdiv-arm,"
|
||||
"+trustzone,+t2xtpk,+crypto,+crc";
|
||||
else
|
||||
// Use CPU to figure out the exact features
|
||||
ARMArchFeature = "+v8";
|
||||
break;
|
||||
case Triple::ARMSubArch_v8_1a:
|
||||
if (NoCPU)
|
||||
// v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP,
|
||||
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
|
||||
// FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
|
||||
ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+dsp,+mp,+hwdiv,+hwdiv-arm,"
|
||||
"+trustzone,+t2xtpk,+crypto,+crc";
|
||||
else
|
||||
// Use CPU to figure out the exact features
|
||||
ARMArchFeature = "+v8.1a";
|
||||
break;
|
||||
case Triple::ARMSubArch_v7m:
|
||||
isThumb = true;
|
||||
if (NoCPU)
|
||||
// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
|
||||
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
|
||||
else
|
||||
// Use CPU to figure out the exact features.
|
||||
ARMArchFeature = "+v7";
|
||||
break;
|
||||
case Triple::ARMSubArch_v7em:
|
||||
if (NoCPU)
|
||||
// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSP,
|
||||
// FeatureT2XtPk, FeatureMClass
|
||||
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+dsp,+t2xtpk,+mclass";
|
||||
else
|
||||
// Use CPU to figure out the exact features.
|
||||
ARMArchFeature = "+v7";
|
||||
break;
|
||||
case Triple::ARMSubArch_v7s:
|
||||
if (NoCPU)
|
||||
// v7s: FeatureNEON, FeatureDB, FeatureDSP, FeatureHasRAS
|
||||
// Swift
|
||||
ARMArchFeature = "+v7,+swift,+neon,+db,+dsp,+ras";
|
||||
else
|
||||
// Use CPU to figure out the exact features.
|
||||
ARMArchFeature = "+v7";
|
||||
break;
|
||||
case Triple::ARMSubArch_v7k:
|
||||
if (NoCPU)
|
||||
// v7k: FeatureNEON, FeatureDB, FeatureDSP, FeatureHasRAS
|
||||
// A7
|
||||
ARMArchFeature = "+v7,+a7,+neon,+db,+dsp,+ras";
|
||||
else
|
||||
// Use CPU to figure out the exact features.
|
||||
ARMArchFeature = "+v7";
|
||||
break;
|
||||
case Triple::ARMSubArch_v7:
|
||||
// v7 CPUs have lots of different feature sets. If no CPU is specified,
|
||||
// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
|
||||
// the "minimum" feature set and use CPU string to figure out the exact
|
||||
// features.
|
||||
if (NoCPU)
|
||||
// v7a: FeatureNEON, FeatureDB, FeatureDSP, FeatureT2XtPk
|
||||
ARMArchFeature = "+v7,+neon,+db,+dsp,+t2xtpk";
|
||||
else
|
||||
// Use CPU to figure out the exact features.
|
||||
ARMArchFeature = "+v7";
|
||||
break;
|
||||
case Triple::ARMSubArch_v6t2:
|
||||
ARMArchFeature = "+v6t2";
|
||||
break;
|
||||
case Triple::ARMSubArch_v6k:
|
||||
ARMArchFeature = "+v6k";
|
||||
break;
|
||||
case Triple::ARMSubArch_v6m:
|
||||
isThumb = true;
|
||||
if (NoCPU)
|
||||
// v6m: FeatureNoARM, FeatureMClass
|
||||
ARMArchFeature = "+v6m,+noarm,+mclass";
|
||||
else
|
||||
ARMArchFeature = "+v6";
|
||||
break;
|
||||
case Triple::ARMSubArch_v6:
|
||||
ARMArchFeature = "+v6";
|
||||
break;
|
||||
case Triple::ARMSubArch_v5te:
|
||||
ARMArchFeature = "+v5te";
|
||||
break;
|
||||
case Triple::ARMSubArch_v5:
|
||||
ARMArchFeature = "+v5t";
|
||||
break;
|
||||
case Triple::ARMSubArch_v4t:
|
||||
ARMArchFeature = "+v4t";
|
||||
break;
|
||||
case Triple::NoSubArch:
|
||||
break;
|
||||
}
|
||||
|
||||
unsigned ArchID = ARM::parseArch(TT.getArchName());
|
||||
if (ArchID != ARM::AK_INVALID && (CPU.empty() || CPU == "generic"))
|
||||
ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
|
||||
|
||||
if (isThumb) {
|
||||
if (ARMArchFeature.empty())
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user