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Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only.
llvm-svn: 96019
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@ -1532,7 +1532,39 @@ multiclass AI_smla<string opc, PatFrag opnode> {
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defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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// TODO: Halfword multiple accumulate long: SMLAL<x><y>
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// Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
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def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
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IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV5TE]> {
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let Inst{5} = 0;
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let Inst{6} = 0;
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}
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def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
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IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV5TE]> {
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let Inst{5} = 0;
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let Inst{6} = 1;
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}
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def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
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IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV5TE]> {
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let Inst{5} = 1;
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let Inst{6} = 0;
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}
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def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
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IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV5TE]> {
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let Inst{5} = 1;
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let Inst{6} = 1;
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}
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// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
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// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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