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[globalisel][tablegen] Tests for r319691
I forgot to 'svn add' the test files. llvm-svn: 319698
This commit is contained in:
Daniel Sanders
parent
218aa3c4c3
commit
a60df77dd5
@ -0,0 +1,91 @@
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# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_load(i8* %addr) {
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entry:
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ret void
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}
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define void @test_store(i8* %addr) {
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entry:
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ret void
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}
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...
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---
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name: test_load
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_load
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%0(p0) = COPY %x0
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; CHECK: %1:_(s8) = G_ATOMIC_LOAD %0(p0) :: (load unordered 1 from %ir.addr)
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%1(s8) = G_ATOMIC_LOAD %0 :: (load unordered 1 from %ir.addr)
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%10:_(s32) = G_ANYEXT %1
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%w0 = COPY %10
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; CHECK: %2:_(s16) = G_ATOMIC_LOAD %0(p0) :: (load unordered 2 from %ir.addr)
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%2(s16) = G_ATOMIC_LOAD %0 :: (load unordered 2 from %ir.addr)
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%11:_(s32) = G_ANYEXT %2
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%w0 = COPY %11
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; CHECK: %3:_(s32) = G_ATOMIC_LOAD %0(p0) :: (load unordered 4 from %ir.addr)
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%3(s32) = G_ATOMIC_LOAD %0 :: (load unordered 4 from %ir.addr)
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%w0 = COPY %3
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; CHECK: %4:_(s64) = G_ATOMIC_LOAD %0(p0) :: (load unordered 8 from %ir.addr)
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%4(s64) = G_ATOMIC_LOAD %0 :: (load unordered 8 from %ir.addr)
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%x0 = COPY %4
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%5(p0) = G_ATOMIC_LOAD %0(p0) :: (load unordered 8 from %ir.addr)
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%12:_(s64) = G_PTRTOINT %5
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%x0 = COPY %12
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...
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---
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name: test_store
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_store
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%0(p0) = COPY %x0
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%1(s32) = COPY %w1
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; CHECK: G_ATOMIC_STORE %2(s8), %0(p0) :: (store unordered 1 into %ir.addr)
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%2(s8) = G_TRUNC %1
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G_ATOMIC_STORE %2, %0 :: (store unordered 1 into %ir.addr)
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; CHECK: G_ATOMIC_STORE %3(s16), %0(p0) :: (store unordered 2 into %ir.addr)
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%3(s16) = G_TRUNC %1
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G_ATOMIC_STORE %3, %0 :: (store unordered 2 into %ir.addr)
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; CHECK: G_ATOMIC_STORE %1(s32), %0(p0) :: (store unordered 4 into %ir.addr)
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G_ATOMIC_STORE %1, %0 :: (store unordered 4 into %ir.addr)
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; CHECK: G_ATOMIC_STORE %4(s64), %0(p0) :: (store unordered 8 into %ir.addr)
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%4(s64) = G_PTRTOINT %0(p0)
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G_ATOMIC_STORE %4, %0 :: (store unordered 8 into %ir.addr)
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; CHECK: G_ATOMIC_STORE %0(p0), %0(p0) :: (store unordered 8 into %ir.addr)
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G_ATOMIC_STORE %0(p0), %0(p0) :: (store unordered 8 into %ir.addr)
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...
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431
test/CodeGen/AArch64/GlobalISel/select-atomic-load.mir
Normal file
431
test/CodeGen/AArch64/GlobalISel/select-atomic-load.mir
Normal file
@ -0,0 +1,431 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @load_s8_gpr_unordered(i64* %addr) { ret void }
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define void @load_s8_gpr_monotonic(i64* %addr) { ret void }
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define void @load_s8_gpr_acquire(i64* %addr) { ret void }
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define void @load_s8_gpr_release(i64* %addr) { ret void }
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define void @load_s8_gpr_acq_rel(i64* %addr) { ret void }
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define void @load_s8_gpr_seq_cst(i64* %addr) { ret void }
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define void @load_s32_gpr_unordered(i64* %addr) { ret void }
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define void @load_s32_gpr_monotonic(i64* %addr) { ret void }
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define void @load_s32_gpr_acquire(i64* %addr) { ret void }
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define void @load_s32_gpr_release(i64* %addr) { ret void }
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define void @load_s32_gpr_acq_rel(i64* %addr) { ret void }
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define void @load_s32_gpr_seq_cst(i64* %addr) { ret void }
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define void @load_s64_gpr_unordered(i64* %addr) { ret void }
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define void @load_s64_gpr_monotonic(i64* %addr) { ret void }
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define void @load_s64_gpr_acquire(i64* %addr) { ret void }
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define void @load_s64_gpr_release(i64* %addr) { ret void }
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define void @load_s64_gpr_acq_rel(i64* %addr) { ret void }
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define void @load_s64_gpr_seq_cst(i64* %addr) { ret void }
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...
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---
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name: load_s8_gpr_unordered
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s8_gpr_unordered
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 4 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s8) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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%x0 = COPY %2(s32)
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...
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---
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name: load_s8_gpr_monotonic
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s8_gpr_monotonic
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 4 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s8) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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%x0 = COPY %2(s32)
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...
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---
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name: load_s8_gpr_acquire
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s8_gpr_acquire
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire 1 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s8) = G_ATOMIC_LOAD %0 :: (load acquire 1 from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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%x0 = COPY %2(s32)
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...
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---
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name: load_s8_gpr_release
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s8_gpr_release
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 1 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s8) = G_ATOMIC_LOAD %0 :: (load release 1 from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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%x0 = COPY %2(s32)
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...
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---
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name: load_s8_gpr_acq_rel
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s8_gpr_acq_rel
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acq_rel 1 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s8) = G_ATOMIC_LOAD %0 :: (load acq_rel 1 from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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%x0 = COPY %2(s32)
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...
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---
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name: load_s8_gpr_seq_cst
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s8_gpr_seq_cst
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst 1 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s8) = G_ATOMIC_LOAD %0 :: (load seq_cst 1 from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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%x0 = COPY %2(s32)
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...
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---
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name: load_s32_gpr_unordered
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s32_gpr_unordered
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
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%x0 = COPY %1(s32)
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...
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---
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name: load_s32_gpr_monotonic
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s32_gpr_monotonic
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
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%x0 = COPY %1(s32)
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...
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---
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name: load_s32_gpr_acquire
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s32_gpr_acquire
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load acquire 4 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s32) = G_ATOMIC_LOAD %0 :: (load acquire 4 from %ir.addr)
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%x0 = COPY %1(s32)
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...
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---
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name: load_s32_gpr_release
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s32_gpr_release
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
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%x0 = COPY %1(s32)
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...
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---
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name: load_s32_gpr_acq_rel
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s32_gpr_acq_rel
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load acq_rel 4 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s32) = G_ATOMIC_LOAD %0 :: (load acq_rel 4 from %ir.addr)
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%x0 = COPY %1(s32)
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...
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---
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name: load_s32_gpr_seq_cst
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s32_gpr_seq_cst
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load seq_cst 4 from %ir.addr)
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; CHECK: %x0 = COPY [[T0]]
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%0(p0) = COPY %x0
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%1(s32) = G_ATOMIC_LOAD %0 :: (load seq_cst 4 from %ir.addr)
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%x0 = COPY %1(s32)
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...
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---
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name: load_s64_gpr_unordered
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: load_s64_gpr_unordered
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr)
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; CHECK: %x0 = COPY [[LDRXui]]
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%0(p0) = COPY %x0
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%1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr)
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%x0 = COPY %1(s64)
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...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_monotonic
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_monotonic
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_acquire
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_acquire
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load acquire 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load acquire 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_release
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_release
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_acq_rel
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_acq_rel
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load acq_rel 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load acq_rel 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_seq_cst
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_seq_cst
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load seq_cst 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load seq_cst 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue
Block a user