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[X86][AVX] Add commutation support for VPERM2X128 instructions
Its main use is to allow memory folding of the 1st operand Differential Revision: http://reviews.llvm.org/D16521 llvm-svn: 258726
This commit is contained in:
Simon Pilgrim
parent
8b2ed4fc5e
commit
a63717e4c0
@ -3275,6 +3275,20 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
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MI->getOperand(3).setImm(Imm);
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MI->getOperand(3).setImm(Imm);
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return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
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return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
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}
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}
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case X86::VPERM2F128rr:
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case X86::VPERM2I128rr: {
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// Flip permute source immediate.
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// Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
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// Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
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unsigned Imm = MI->getOperand(3).getImm() & 0xFF;
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if (NewMI) {
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MachineFunction &MF = *MI->getParent()->getParent();
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MI = MF.CloneMachineInstr(MI);
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NewMI = false;
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}
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MI->getOperand(3).setImm(Imm ^ 0x22);
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return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
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}
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case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
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case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
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case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
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case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
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case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
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case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
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@ -8158,6 +8158,7 @@ def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
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// VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
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// VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
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//
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//
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let ExeDomain = SSEPackedSingle in {
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let ExeDomain = SSEPackedSingle in {
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let isCommutable = 1 in
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def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
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def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, u8imm:$src3),
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(ins VR256:$src1, VR256:$src2, u8imm:$src3),
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"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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@ -8531,6 +8532,7 @@ defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
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// VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
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//
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//
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let isCommutable = 1 in
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def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
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def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, u8imm:$src3),
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(ins VR256:$src1, VR256:$src2, u8imm:$src3),
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"vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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"vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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@ -366,3 +366,174 @@ define <4 x i64> @vperm2z_int_0x83(<4 x i64> %a, <4 x i64> %b) {
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ret <4 x i64> %c
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ret <4 x i64> %c
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}
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}
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;;; Memory folding cases
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define <4 x double> @ld0_hi0_lo1_4f64(<4 x double> * %pa, <4 x double> %b) nounwind uwtable readnone ssp {
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; AVX1-LABEL: ld0_hi0_lo1_4f64:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
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; AVX1-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ld0_hi0_lo1_4f64:
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; AVX2: ## BB#0: ## %entry
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; AVX2-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
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; AVX2-NEXT: vbroadcastsd {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vaddpd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%a = load <4 x double>, <4 x double> * %pa
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
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%res = fadd <4 x double> %shuffle, <double 1.0, double 1.0, double 1.0, double 1.0>
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ret <4 x double> %res
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}
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define <4 x double> @ld1_hi0_hi1_4f64(<4 x double> %a, <4 x double> * %pb) nounwind uwtable readnone ssp {
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; AVX1-LABEL: ld1_hi0_hi1_4f64:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]
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; AVX1-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ld1_hi0_hi1_4f64:
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; AVX2: ## BB#0: ## %entry
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; AVX2-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]
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; AVX2-NEXT: vbroadcastsd {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vaddpd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%b = load <4 x double>, <4 x double> * %pb
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
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%res = fadd <4 x double> %shuffle, <double 1.0, double 1.0, double 1.0, double 1.0>
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ret <4 x double> %res
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}
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define <8 x float> @ld0_hi0_lo1_8f32(<8 x float> * %pa, <8 x float> %b) nounwind uwtable readnone ssp {
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; AVX1-LABEL: ld0_hi0_lo1_8f32:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
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; AVX1-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ld0_hi0_lo1_8f32:
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; AVX2: ## BB#0: ## %entry
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; AVX2-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
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; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vaddps %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%a = load <8 x float>, <8 x float> * %pa
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
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%res = fadd <8 x float> %shuffle, <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
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ret <8 x float> %res
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}
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define <8 x float> @ld1_hi0_hi1_8f32(<8 x float> %a, <8 x float> * %pb) nounwind uwtable readnone ssp {
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; AVX1-LABEL: ld1_hi0_hi1_8f32:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]
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; AVX1-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ld1_hi0_hi1_8f32:
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; AVX2: ## BB#0: ## %entry
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; AVX2-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]
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; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vaddps %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%b = load <8 x float>, <8 x float> * %pb
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
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%res = fadd <8 x float> %shuffle, <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
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ret <8 x float> %res
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}
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define <4 x i64> @ld0_hi0_lo1_4i64(<4 x i64> * %pa, <4 x i64> %b) nounwind uwtable readnone ssp {
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; AVX1-LABEL: ld0_hi0_lo1_4i64:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
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; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ld0_hi0_lo1_4i64:
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; AVX2: ## BB#0: ## %entry
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; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
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; AVX2-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%a = load <4 x i64>, <4 x i64> * %pa
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
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%res = add <4 x i64> %shuffle, <i64 1, i64 2, i64 3, i64 4>
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ret <4 x i64> %res
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}
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define <4 x i64> @ld1_hi0_hi1_4i64(<4 x i64> %a, <4 x i64> * %pb) nounwind uwtable readnone ssp {
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; AVX1-LABEL: ld1_hi0_hi1_4i64:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]
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; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ld1_hi0_hi1_4i64:
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; AVX2: ## BB#0: ## %entry
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; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]
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; AVX2-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%b = load <4 x i64>, <4 x i64> * %pb
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
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%res = add <4 x i64> %shuffle, <i64 1, i64 2, i64 3, i64 4>
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ret <4 x i64> %res
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}
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define <8 x i32> @ld0_hi0_lo1_8i32(<8 x i32> * %pa, <8 x i32> %b) nounwind uwtable readnone ssp {
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; AVX1-LABEL: ld0_hi0_lo1_8i32:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,2,3,4]
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; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ld0_hi0_lo1_8i32:
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; AVX2: ## BB#0: ## %entry
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; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
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; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%a = load <8 x i32>, <8 x i32> * %pa
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%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
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%res = add <8 x i32> %shuffle, <i32 1, i32 2, i32 3, i32 4, i32 1, i32 2, i32 3, i32 4>
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ret <8 x i32> %res
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}
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define <8 x i32> @ld1_hi0_hi1_8i32(<8 x i32> %a, <8 x i32> * %pb) nounwind uwtable readnone ssp {
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; AVX1-LABEL: ld1_hi0_hi1_8i32:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,2,3,4]
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; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ld1_hi0_hi1_8i32:
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; AVX2: ## BB#0: ## %entry
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; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]
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; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%b = load <8 x i32>, <8 x i32> * %pb
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%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
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%res = add <8 x i32> %shuffle, <i32 1, i32 2, i32 3, i32 4, i32 1, i32 2, i32 3, i32 4>
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ret <8 x i32> %res
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}
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