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[FPEnv][X86] Constrained FCmp intrinsics enabling on X86
Summary: This is a follow up of D69281, it enables the X86 backend support for the FP comparision. Reviewers: uweigand, kpn, craig.topper, RKSimon, cameron.mcinally, andrew.w.kaylor Subscribers: hiraditya, llvm-commits, annita.zhang, LuoYuanke, LiuChen3 Tags: #llvm Differential Revision: https://reviews.llvm.org/D70582
This commit is contained in:
Wang, Pengfei
parent
e065d8f1ac
commit
a6543a42ec
@ -983,13 +983,17 @@ public:
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/// Helper function to make it easier to build SetCC's if you just have an
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/// ISD::CondCode instead of an SDValue.
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SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS,
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ISD::CondCode Cond) {
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ISD::CondCode Cond, SDValue Chain = SDValue(),
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bool IsSignaling = false) {
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assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&
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"Cannot compare scalars to vectors");
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assert(LHS.getValueType().isVector() == VT.isVector() &&
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"Cannot compare scalars to vectors");
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assert(Cond != ISD::SETCC_INVALID &&
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"Cannot create a setCC of an invalid node.");
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if (Chain)
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return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
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{VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
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return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
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}
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@ -134,7 +134,8 @@ private:
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ArrayRef<int> Mask) const;
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bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
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bool &NeedInvert, const SDLoc &dl);
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bool &NeedInvert, const SDLoc &dl, SDValue &Chain,
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bool IsSignaling = false);
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SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
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@ -1638,10 +1639,9 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
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/// of a true/false result.
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///
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/// \returns true if the SetCC has been legalized, false if it hasn't.
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bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
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SDValue &RHS, SDValue &CC,
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bool &NeedInvert,
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const SDLoc &dl) {
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bool SelectionDAGLegalize::LegalizeSetCCCondCode(
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EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, bool &NeedInvert,
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const SDLoc &dl, SDValue &Chain, bool IsSignaling) {
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MVT OpVT = LHS.getSimpleValueType();
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ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
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NeedInvert = false;
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@ -1724,13 +1724,16 @@ bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
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if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
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// If we aren't the ordered or unorder operation,
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// then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
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SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
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SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
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SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling);
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SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2, Chain, IsSignaling);
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} else {
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// Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
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SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
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SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
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SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling);
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SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2, Chain, IsSignaling);
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}
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if (Chain)
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, SetCC1.getValue(1),
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SetCC2.getValue(1));
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LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
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RHS = SDValue();
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CC = SDValue();
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@ -3524,12 +3527,19 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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}
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Results.push_back(Tmp1);
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break;
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case ISD::SETCC: {
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Tmp1 = Node->getOperand(0);
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Tmp2 = Node->getOperand(1);
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Tmp3 = Node->getOperand(2);
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bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
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Tmp3, NeedInvert, dl);
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case ISD::SETCC:
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case ISD::STRICT_FSETCC:
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case ISD::STRICT_FSETCCS: {
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bool IsStrict = Node->getOpcode() != ISD::SETCC;
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bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS;
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SDValue Chain = IsStrict ? Node->getOperand(0) : SDValue();
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unsigned Offset = IsStrict ? 1 : 0;
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Tmp1 = Node->getOperand(0 + Offset);
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Tmp2 = Node->getOperand(1 + Offset);
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Tmp3 = Node->getOperand(2 + Offset);
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bool Legalized =
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LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3,
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NeedInvert, dl, Chain, IsSignaling);
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if (Legalized) {
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// If we expanded the SETCC by swapping LHS and RHS, or by inverting the
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@ -3544,9 +3554,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
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Results.push_back(Tmp1);
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if (IsStrict)
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Results.push_back(Chain);
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break;
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}
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// FIXME: It seems Legalized is false iff CCCode is Legal. I don't
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// understand if this code is useful for strict nodes.
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assert(!IsStrict && "Don't know how to expand for strict nodes.");
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// Otherwise, SETCC for the given comparison type must be completely
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// illegal; expand it into a SELECT_CC.
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EVT VT = Node->getValueType(0);
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@ -3569,11 +3586,13 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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break;
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}
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case ISD::SELECT_CC: {
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// TODO: need to add STRICT_SELECT_CC and STRICT_SELECT_CCS
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Tmp1 = Node->getOperand(0); // LHS
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Tmp2 = Node->getOperand(1); // RHS
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Tmp3 = Node->getOperand(2); // True
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Tmp4 = Node->getOperand(3); // False
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EVT VT = Node->getValueType(0);
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SDValue Chain;
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SDValue CC = Node->getOperand(4);
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ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
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@ -3616,9 +3635,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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}
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if (!Legalized) {
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Legalized = LegalizeSetCCCondCode(
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getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
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dl);
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Legalized = LegalizeSetCCCondCode(getSetCCResultType(Tmp1.getValueType()),
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Tmp1, Tmp2, CC, NeedInvert, dl, Chain);
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assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
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@ -3644,13 +3662,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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break;
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}
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case ISD::BR_CC: {
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// TODO: need to add STRICT_BR_CC and STRICT_BR_CCS
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SDValue Chain;
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Tmp1 = Node->getOperand(0); // Chain
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Tmp2 = Node->getOperand(2); // LHS
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Tmp3 = Node->getOperand(3); // RHS
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Tmp4 = Node->getOperand(1); // CC
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bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
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Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
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bool Legalized =
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LegalizeSetCCCondCode(getSetCCResultType(Tmp2.getValueType()), Tmp2,
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Tmp3, Tmp4, NeedInvert, dl, Chain);
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(void)Legalized;
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assert(Legalized && "Can't legalize BR_CC with legal condition!");
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@ -667,6 +667,12 @@ static const TableEntry OpcodeTable[] = {
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{ X86::CMOVP_Fp32 , X86::CMOVP_F },
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{ X86::CMOVP_Fp64 , X86::CMOVP_F },
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{ X86::CMOVP_Fp80 , X86::CMOVP_F },
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{ X86::COM_FpIr32 , X86::COM_FIr },
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{ X86::COM_FpIr64 , X86::COM_FIr },
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{ X86::COM_FpIr80 , X86::COM_FIr },
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{ X86::COM_Fpr32 , X86::COM_FST0r },
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{ X86::COM_Fpr64 , X86::COM_FST0r },
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{ X86::COM_Fpr80 , X86::COM_FST0r },
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{ X86::DIVR_Fp32m , X86::DIVR_F32m },
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{ X86::DIVR_Fp64m , X86::DIVR_F64m },
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{ X86::DIVR_Fp64m32 , X86::DIVR_F32m },
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@ -798,6 +804,10 @@ static unsigned getConcreteOpcode(unsigned Opcode) {
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static const TableEntry PopTable[] = {
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{ X86::ADD_FrST0 , X86::ADD_FPrST0 },
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{ X86::COMP_FST0r, X86::FCOMPP },
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{ X86::COM_FIr , X86::COM_FIPr },
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{ X86::COM_FST0r , X86::COMP_FST0r },
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{ X86::DIVR_FrST0, X86::DIVR_FPrST0 },
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{ X86::DIV_FrST0 , X86::DIV_FPrST0 },
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@ -836,7 +846,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
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int Opcode = Lookup(PopTable, I->getOpcode());
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if (Opcode != -1) {
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I->setDesc(TII->get(Opcode));
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if (Opcode == X86::UCOM_FPPr)
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if (Opcode == X86::FCOMPP || Opcode == X86::UCOM_FPPr)
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I->RemoveOperand(0);
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} else { // Insert an explicit pop
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I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
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@ -542,6 +542,10 @@ static bool isLegalMaskCompare(SDNode *N, const X86Subtarget *Subtarget) {
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// this happens we will use 512-bit operations and the mask will not be
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// zero extended.
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EVT OpVT = N->getOperand(0).getValueType();
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// The first operand of X86ISD::CMPM is chain, so we need to get the second
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// operand.
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if (Opcode == X86ISD::CMPM)
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OpVT = N->getOperand(1).getValueType();
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if (OpVT.is256BitVector() || OpVT.is128BitVector())
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return Subtarget->hasVLX();
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@ -410,6 +410,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
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}
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for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
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if (VT == MVT::i64 && !Subtarget.is64Bit())
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@ -929,6 +931,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
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setOperationAction(ISD::CTPOP, VT, Custom);
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setOperationAction(ISD::ABS, VT, Custom);
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@ -1212,6 +1216,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
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setOperationAction(ISD::CTPOP, VT, Custom);
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setOperationAction(ISD::CTLZ, VT, Custom);
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@ -1374,6 +1380,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SUB, VT, Custom);
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setOperationAction(ISD::MUL, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::TRUNCATE, VT, Custom);
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setOperationAction(ISD::UADDSAT, VT, Custom);
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@ -1513,6 +1521,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::ROTL, VT, Custom);
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setOperationAction(ISD::ROTR, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
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setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
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setOperationAction(ISD::SELECT, VT, Custom);
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// The condition codes aren't legal in SSE/AVX and under AVX512 we use
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@ -20264,14 +20274,20 @@ static SDValue EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
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/// Emit nodes that will be selected as "cmp Op0,Op1", or something
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/// equivalent.
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SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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const SDLoc &dl, SelectionDAG &DAG) const {
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const SDLoc &dl, SelectionDAG &DAG,
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SDValue Chain, bool IsSignaling) const {
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if (isNullConstant(Op1))
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return EmitTest(Op0, X86CC, dl, DAG, Subtarget);
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EVT CmpVT = Op0.getValueType();
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if (CmpVT.isFloatingPoint())
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if (CmpVT.isFloatingPoint()) {
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if (Chain)
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return DAG.getNode(IsSignaling ? X86ISD::STRICT_FCMPS
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: X86ISD::STRICT_FCMP,
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dl, {MVT::i32, MVT::Other}, {Chain, Op0, Op1});
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
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}
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assert((CmpVT == MVT::i8 || CmpVT == MVT::i16 ||
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CmpVT == MVT::i32 || CmpVT == MVT::i64) && "Unexpected VT!");
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@ -20333,16 +20349,19 @@ SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
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SelectionDAG &DAG) const {
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// If the subtarget does not support the FUCOMI instruction, floating-point
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// comparisons have to be converted.
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if (Subtarget.hasCMov() ||
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Cmp.getOpcode() != X86ISD::CMP ||
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!Cmp.getOperand(0).getValueType().isFloatingPoint() ||
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!Cmp.getOperand(1).getValueType().isFloatingPoint())
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bool IsCmp = Cmp.getOpcode() == X86ISD::CMP;
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bool IsStrictCmp = Cmp.getOpcode() == X86ISD::STRICT_FCMP ||
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Cmp.getOpcode() == X86ISD::STRICT_FCMPS;
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if (Subtarget.hasCMov() || (!IsCmp && !IsStrictCmp) ||
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!Cmp.getOperand(IsStrictCmp ? 1 : 0).getValueType().isFloatingPoint() ||
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!Cmp.getOperand(IsStrictCmp ? 2 : 1).getValueType().isFloatingPoint())
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return Cmp;
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// The instruction selector will select an FUCOM instruction instead of
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// FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
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// build an SDNode sequence that transfers the result from FPSW into EFLAGS:
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// (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
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// (X86sahf (trunc (srl (X86fp_stsw (trunc (X86any_fcmp ...)), 8))))
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SDLoc dl(Cmp);
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SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
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SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
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@ -20586,7 +20605,7 @@ static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC,
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/// Turns an ISD::CondCode into a value suitable for SSE floating-point mask
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/// CMPs.
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static unsigned translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
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SDValue &Op1) {
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SDValue &Op1, bool &IsAlwaysSignaling) {
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unsigned SSECC;
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bool Swap = false;
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@ -20625,6 +20644,22 @@ static unsigned translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
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if (Swap)
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std::swap(Op0, Op1);
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switch (SetCCOpcode) {
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default:
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IsAlwaysSignaling = true;
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break;
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case ISD::SETEQ:
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case ISD::SETOEQ:
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case ISD::SETUEQ:
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case ISD::SETNE:
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case ISD::SETONE:
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case ISD::SETUNE:
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case ISD::SETO:
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case ISD::SETUO:
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IsAlwaysSignaling = false;
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break;
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}
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return SSECC;
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}
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@ -20769,12 +20804,16 @@ static SDValue LowerVSETCCWithSUBUS(SDValue Op0, SDValue Op1, MVT VT,
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static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
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SelectionDAG &DAG) {
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SDValue Op0 = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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SDValue CC = Op.getOperand(2);
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MVT VT = Op.getSimpleValueType();
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bool IsStrict = Op.getOpcode() == ISD::STRICT_FSETCC ||
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Op.getOpcode() == ISD::STRICT_FSETCCS;
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bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS;
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SDValue Chain = IsStrict ? Op.getOperand(0) : DAG.getEntryNode();
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SDValue Op0 = Op.getOperand(IsStrict ? 1 : 0);
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SDValue Op1 = Op.getOperand(IsStrict ? 2 : 1);
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SDValue CC = Op.getOperand(IsStrict ? 3 : 2);
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MVT VT = Op->getSimpleValueType(0);
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ISD::CondCode Cond = cast<CondCodeSDNode>(CC)->get();
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bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
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bool isFP = Op1.getSimpleValueType().isFloatingPoint();
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SDLoc dl(Op);
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if (isFP) {
|
||||
@ -20795,34 +20834,74 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
|
||||
VT = Op0.getSimpleValueType();
|
||||
}
|
||||
|
||||
// In the two cases not handled by SSE compare predicates (SETUEQ/SETONE),
|
||||
// emit two comparisons and a logic op to tie them together.
|
||||
SDValue Cmp;
|
||||
unsigned SSECC = translateX86FSETCC(Cond, Op0, Op1);
|
||||
if (SSECC >= 8 && !Subtarget.hasAVX()) {
|
||||
// LLVM predicate is SETUEQ or SETONE.
|
||||
unsigned CC0, CC1;
|
||||
unsigned CombineOpc;
|
||||
if (Cond == ISD::SETUEQ) {
|
||||
CC0 = 3; // UNORD
|
||||
CC1 = 0; // EQ
|
||||
CombineOpc = X86ISD::FOR;
|
||||
} else {
|
||||
assert(Cond == ISD::SETONE);
|
||||
CC0 = 7; // ORD
|
||||
CC1 = 4; // NEQ
|
||||
CombineOpc = X86ISD::FAND;
|
||||
bool IsAlwaysSignaling;
|
||||
unsigned SSECC = translateX86FSETCC(Cond, Op0, Op1, IsAlwaysSignaling);
|
||||
if (!Subtarget.hasAVX()) {
|
||||
// TODO: We could use following steps to handle a quiet compare with
|
||||
// signaling encodings.
|
||||
// 1. Get ordered masks from a quiet ISD::SETO
|
||||
// 2. Use the masks to mask potential unordered elements in operand A, B
|
||||
// 3. Get the compare results of masked A, B
|
||||
// 4. Calculating final result using the mask and result from 3
|
||||
// But currently, we just fall back to scalar operations.
|
||||
if (IsStrict && IsAlwaysSignaling && !IsSignaling)
|
||||
return SDValue();
|
||||
|
||||
// Insert an extra signaling instruction to raise exception.
|
||||
if (IsStrict && !IsAlwaysSignaling && IsSignaling) {
|
||||
SDValue SignalCmp = DAG.getNode(
|
||||
Opc, dl, {VT, MVT::Other},
|
||||
{Chain, Op0, Op1, DAG.getTargetConstant(1, dl, MVT::i8)}); // LT_OS
|
||||
// FIXME: It seems we need to update the flags of all new strict nodes.
|
||||
// Otherwise, mayRaiseFPException in MI will return false due to
|
||||
// NoFPExcept = false by default. However, I didn't find it in other
|
||||
// patches.
|
||||
SignalCmp->setFlags(Op->getFlags());
|
||||
Chain = SignalCmp.getValue(1);
|
||||
}
|
||||
|
||||
SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
|
||||
DAG.getTargetConstant(CC0, dl, MVT::i8));
|
||||
SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
|
||||
DAG.getTargetConstant(CC1, dl, MVT::i8));
|
||||
Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
|
||||
// In the two cases not handled by SSE compare predicates (SETUEQ/SETONE),
|
||||
// emit two comparisons and a logic op to tie them together.
|
||||
if (SSECC >= 8) {
|
||||
// LLVM predicate is SETUEQ or SETONE.
|
||||
unsigned CC0, CC1;
|
||||
unsigned CombineOpc;
|
||||
if (Cond == ISD::SETUEQ) {
|
||||
CC0 = 3; // UNORD
|
||||
CC1 = 0; // EQ
|
||||
CombineOpc = X86ISD::FOR;
|
||||
} else {
|
||||
assert(Cond == ISD::SETONE);
|
||||
CC0 = 7; // ORD
|
||||
CC1 = 4; // NEQ
|
||||
CombineOpc = X86ISD::FAND;
|
||||
}
|
||||
|
||||
SDValue Cmp0 = DAG.getNode(
|
||||
Opc, dl, {VT, MVT::Other},
|
||||
{Chain, Op0, Op1, DAG.getTargetConstant(CC0, dl, MVT::i8)});
|
||||
SDValue Cmp1 = DAG.getNode(
|
||||
Opc, dl, {VT, MVT::Other},
|
||||
{Chain, Op0, Op1, DAG.getTargetConstant(CC1, dl, MVT::i8)});
|
||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Cmp0.getValue(1),
|
||||
Cmp1.getValue(1));
|
||||
Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
|
||||
} else {
|
||||
Cmp = DAG.getNode(
|
||||
Opc, dl, {VT, MVT::Other},
|
||||
{Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)});
|
||||
Chain = Cmp.getValue(1);
|
||||
}
|
||||
} else {
|
||||
// Handle all other FP comparisons here.
|
||||
Cmp = DAG.getNode(Opc, dl, VT, Op0, Op1,
|
||||
DAG.getTargetConstant(SSECC, dl, MVT::i8));
|
||||
if (IsStrict)
|
||||
// Make a flip on already signaling CCs before setting bit 4 of AVX CC.
|
||||
SSECC |= (IsAlwaysSignaling ^ IsSignaling) << 4;
|
||||
Cmp = DAG.getNode(
|
||||
Opc, dl, {VT, MVT::Other},
|
||||
{Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)});
|
||||
Chain = Cmp.getValue(1);
|
||||
}
|
||||
|
||||
// If this is SSE/AVX CMPP, bitcast the result back to integer to match the
|
||||
@ -20831,9 +20910,14 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
|
||||
if (Opc == X86ISD::CMPP)
|
||||
Cmp = DAG.getBitcast(Op.getSimpleValueType(), Cmp);
|
||||
|
||||
if (IsStrict)
|
||||
return DAG.getMergeValues({Cmp, Chain}, dl);
|
||||
|
||||
return Cmp;
|
||||
}
|
||||
|
||||
assert(!IsStrict && "Strict SETCC only handles FP operands.");
|
||||
|
||||
MVT VTOp0 = Op0.getSimpleValueType();
|
||||
(void)VTOp0;
|
||||
assert(VTOp0 == Op1.getSimpleValueType() &&
|
||||
@ -21143,8 +21227,9 @@ static SDValue EmitAVX512Test(SDValue Op0, SDValue Op1, ISD::CondCode CC,
|
||||
/// corresponding X86 condition code constant in X86CC.
|
||||
SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
|
||||
ISD::CondCode CC, const SDLoc &dl,
|
||||
SelectionDAG &DAG,
|
||||
SDValue &X86CC) const {
|
||||
SelectionDAG &DAG, SDValue &X86CC,
|
||||
SDValue &Chain,
|
||||
bool IsSignaling) const {
|
||||
// Optimize to BT if possible.
|
||||
// Lower (X & (1 << N)) == 0 to BT(X, N).
|
||||
// Lower ((X >>u N) & 1) != 0 to BT(X, N).
|
||||
@ -21192,7 +21277,9 @@ SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
|
||||
if (CondCode == X86::COND_INVALID)
|
||||
return SDValue();
|
||||
|
||||
SDValue EFLAGS = EmitCmp(Op0, Op1, CondCode, dl, DAG);
|
||||
SDValue EFLAGS = EmitCmp(Op0, Op1, CondCode, dl, DAG, Chain, IsSignaling);
|
||||
if (Chain)
|
||||
Chain = EFLAGS.getValue(1);
|
||||
EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
|
||||
X86CC = DAG.getTargetConstant(CondCode, dl, MVT::i8);
|
||||
return EFLAGS;
|
||||
@ -21200,19 +21287,26 @@ SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
|
||||
|
||||
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
bool IsStrict = Op.getOpcode() == ISD::STRICT_FSETCC ||
|
||||
Op.getOpcode() == ISD::STRICT_FSETCCS;
|
||||
MVT VT = Op->getSimpleValueType(0);
|
||||
|
||||
if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
|
||||
|
||||
assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
|
||||
SDValue Op0 = Op.getOperand(0);
|
||||
SDValue Op1 = Op.getOperand(1);
|
||||
SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
|
||||
SDValue Op0 = Op.getOperand(IsStrict ? 1 : 0);
|
||||
SDValue Op1 = Op.getOperand(IsStrict ? 2 : 1);
|
||||
SDLoc dl(Op);
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
|
||||
ISD::CondCode CC =
|
||||
cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
|
||||
|
||||
// Handle f128 first, since one possible outcome is a normal integer
|
||||
// comparison which gets handled by emitFlagsForSetcc.
|
||||
if (Op0.getValueType() == MVT::f128) {
|
||||
// FIXME: We may need a strict version of softenSetCCOperands before
|
||||
// supporting f128.
|
||||
assert(!IsStrict && "Unhandled strict operation!");
|
||||
softenSetCCOperands(DAG, MVT::f128, Op0, Op1, CC, dl, Op0, Op1);
|
||||
|
||||
// If softenSetCCOperands returned a scalar, use it.
|
||||
@ -21224,11 +21318,17 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
|
||||
}
|
||||
|
||||
SDValue X86CC;
|
||||
SDValue EFLAGS = emitFlagsForSetcc(Op0, Op1, CC, dl, DAG, X86CC);
|
||||
SDValue EFLAGS = emitFlagsForSetcc(Op0, Op1, CC, dl, DAG, X86CC, Chain,
|
||||
Op.getOpcode() == ISD::STRICT_FSETCCS);
|
||||
if (!EFLAGS)
|
||||
return SDValue();
|
||||
|
||||
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS);
|
||||
SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS);
|
||||
|
||||
if (IsStrict)
|
||||
return DAG.getMergeValues({Res, Chain}, dl);
|
||||
|
||||
return Res;
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const {
|
||||
@ -21359,8 +21459,10 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
|
||||
(Subtarget.hasSSE1() && VT == MVT::f32)) &&
|
||||
VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
|
||||
SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
|
||||
unsigned SSECC = translateX86FSETCC(
|
||||
cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
|
||||
bool IsAlwaysSignaling;
|
||||
unsigned SSECC =
|
||||
translateX86FSETCC(cast<CondCodeSDNode>(Cond.getOperand(2))->get(),
|
||||
CondOp0, CondOp1, IsAlwaysSignaling);
|
||||
|
||||
if (Subtarget.hasAVX512()) {
|
||||
SDValue Cmp =
|
||||
@ -21449,7 +21551,9 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
|
||||
}
|
||||
}
|
||||
|
||||
if (Cond.getOpcode() == ISD::SETCC) {
|
||||
if (Cond.getOpcode() == ISD::SETCC ||
|
||||
Cond.getOpcode() == ISD::STRICT_FSETCC ||
|
||||
Cond.getOpcode() == ISD::STRICT_FSETCCS) {
|
||||
if (SDValue NewCond = LowerSETCC(Cond, DAG)) {
|
||||
Cond = NewCond;
|
||||
// If the condition was updated, it's possible that the operands of the
|
||||
@ -22924,6 +23028,24 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
unsigned IntNo = Op.getConstantOperandVal(0);
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
|
||||
|
||||
// We share some nodes between STRICT and non STRICT FP intrinsics.
|
||||
// For these nodes, we need chain them to entry token if they are not called
|
||||
// by STRICT FP intrinsics.
|
||||
auto getProperNode = [&](unsigned Opcode, EVT VT, ArrayRef<SDValue> Ops) {
|
||||
switch (Opcode) {
|
||||
default:
|
||||
return DAG.getNode(Opcode, dl, VT, Ops);
|
||||
case X86ISD::CMPP:
|
||||
case X86ISD::CMPM:
|
||||
break;
|
||||
}
|
||||
|
||||
SmallVector<SDValue, 6> NewOps = {DAG.getEntryNode()};
|
||||
NewOps.append(Ops.begin(), Ops.end());
|
||||
return DAG.getNode(Opcode, dl, {VT, MVT::Other}, NewOps);
|
||||
};
|
||||
|
||||
if (IntrData) {
|
||||
switch(IntrData->Type) {
|
||||
case INTR_TYPE_1OP: {
|
||||
@ -23012,8 +23134,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(),
|
||||
Src1, Src2, Src3);
|
||||
return getProperNode(IntrData->Opc0, Op.getValueType(),
|
||||
{Src1, Src2, Src3});
|
||||
}
|
||||
case INTR_TYPE_4OP:
|
||||
return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
|
||||
@ -23261,8 +23383,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
return SDValue();
|
||||
}
|
||||
//default rounding mode
|
||||
return DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
|
||||
Op.getOperand(2), CC);
|
||||
return getProperNode(IntrData->Opc0, MaskVT,
|
||||
{Op.getOperand(1), Op.getOperand(2), CC});
|
||||
}
|
||||
case CMP_MASK_SCALAR_CC: {
|
||||
SDValue Src1 = Op.getOperand(1);
|
||||
@ -27902,7 +28024,9 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
|
||||
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
|
||||
case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
|
||||
case ISD::SETCC: return LowerSETCC(Op, DAG);
|
||||
case ISD::SETCC:
|
||||
case ISD::STRICT_FSETCC:
|
||||
case ISD::STRICT_FSETCCS: return LowerSETCC(Op, DAG);
|
||||
case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG);
|
||||
case ISD::SELECT: return LowerSELECT(Op, DAG);
|
||||
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
||||
@ -28804,6 +28928,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
case X86ISD::CALL: return "X86ISD::CALL";
|
||||
case X86ISD::BT: return "X86ISD::BT";
|
||||
case X86ISD::CMP: return "X86ISD::CMP";
|
||||
case X86ISD::STRICT_FCMP: return "X86ISD::STRICT_FCMP";
|
||||
case X86ISD::STRICT_FCMPS: return "X86ISD::STRICT_FCMPS";
|
||||
case X86ISD::COMI: return "X86ISD::COMI";
|
||||
case X86ISD::UCOMI: return "X86ISD::UCOMI";
|
||||
case X86ISD::CMPM: return "X86ISD::CMPM";
|
||||
|
||||
@ -79,6 +79,9 @@ namespace llvm {
|
||||
/// X86 compare and logical compare instructions.
|
||||
CMP, COMI, UCOMI,
|
||||
|
||||
/// X86 strict FP compare instructions.
|
||||
STRICT_FCMP, STRICT_FCMPS,
|
||||
|
||||
/// X86 bit-test instructions.
|
||||
BT,
|
||||
|
||||
@ -1340,6 +1343,7 @@ namespace llvm {
|
||||
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
||||
@ -1480,17 +1484,18 @@ namespace llvm {
|
||||
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
|
||||
/// equivalent, for use with the given x86 condition code.
|
||||
SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl,
|
||||
SelectionDAG &DAG) const;
|
||||
SelectionDAG &DAG, SDValue Chain = SDValue(),
|
||||
bool IsSignaling = false) const;
|
||||
|
||||
/// Convert a comparison if required by the subtarget.
|
||||
SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
|
||||
|
||||
/// Emit flags for the given setcc condition and operands. Also returns the
|
||||
/// corresponding X86 condition code constant in X86CC.
|
||||
SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1,
|
||||
ISD::CondCode CC, const SDLoc &dl,
|
||||
SelectionDAG &DAG,
|
||||
SDValue &X86CC) const;
|
||||
SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1, ISD::CondCode CC,
|
||||
const SDLoc &dl, SelectionDAG &DAG,
|
||||
SDValue &X86CC, SDValue &Chain,
|
||||
bool IsSignaling) const;
|
||||
|
||||
/// Check if replacement of SQRT with RSQRT should be disabled.
|
||||
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override;
|
||||
|
||||
@ -8719,20 +8719,18 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in {
|
||||
}
|
||||
|
||||
let Defs = [EFLAGS], Predicates = [HasAVX512] in {
|
||||
defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
|
||||
defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86any_fcmp, f32, f32mem, loadf32,
|
||||
"ucomiss", SSEPackedSingle>, PS, EVEX, VEX_LIG,
|
||||
EVEX_CD8<32, CD8VT1>;
|
||||
defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
|
||||
defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86any_fcmp, f64, f64mem, loadf64,
|
||||
"ucomisd", SSEPackedDouble>, PD, EVEX,
|
||||
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
|
||||
let Pattern = []<dag> in {
|
||||
defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
|
||||
"comiss", SSEPackedSingle>, PS, EVEX, VEX_LIG,
|
||||
EVEX_CD8<32, CD8VT1>;
|
||||
defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
|
||||
"comisd", SSEPackedDouble>, PD, EVEX,
|
||||
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
|
||||
}
|
||||
defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, X86strict_fcmps, f32, f32mem, loadf32,
|
||||
"comiss", SSEPackedSingle>, PS, EVEX, VEX_LIG,
|
||||
EVEX_CD8<32, CD8VT1>;
|
||||
defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, X86strict_fcmps, f64, f64mem, loadf64,
|
||||
"comisd", SSEPackedDouble>, PD, EVEX,
|
||||
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
|
||||
let isCodeGenOnly = 1 in {
|
||||
defm VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem,
|
||||
sse_load_f32, "ucomiss", SSEPackedSingle>, PS, EVEX, VEX_LIG,
|
||||
|
||||
@ -637,11 +637,17 @@ def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
|
||||
// Floating point compares.
|
||||
let SchedRW = [WriteFCom], Uses = [FPCW] in {
|
||||
def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>;
|
||||
[(set FPSW, (trunc (X86any_fcmp RFP32:$lhs, RFP32:$rhs)))]>;
|
||||
def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>;
|
||||
[(set FPSW, (trunc (X86any_fcmp RFP64:$lhs, RFP64:$rhs)))]>;
|
||||
def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>;
|
||||
[(set FPSW, (trunc (X86any_fcmp RFP80:$lhs, RFP80:$rhs)))]>;
|
||||
def COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(set FPSW, (trunc (X86strict_fcmps RFP32:$lhs, RFP32:$rhs)))]>;
|
||||
def COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(set FPSW, (trunc (X86strict_fcmps RFP64:$lhs, RFP64:$rhs)))]>;
|
||||
def COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[(set FPSW, (trunc (X86strict_fcmps RFP80:$lhs, RFP80:$rhs)))]>;
|
||||
} // SchedRW
|
||||
} // mayRaiseFPException = 1
|
||||
|
||||
@ -649,13 +655,22 @@ let SchedRW = [WriteFCom], mayRaiseFPException = 1 in {
|
||||
// CC = ST(0) cmp ST(i)
|
||||
let Defs = [EFLAGS, FPCW], Uses = [FPCW] in {
|
||||
def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>,
|
||||
[(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>,
|
||||
Requires<[FPStackf32, HasCMov]>;
|
||||
def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>,
|
||||
[(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>,
|
||||
Requires<[FPStackf64, HasCMov]>;
|
||||
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>,
|
||||
[(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>,
|
||||
Requires<[HasCMov]>;
|
||||
def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>,
|
||||
Requires<[FPStackf32, HasCMov]>;
|
||||
def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>,
|
||||
Requires<[FPStackf64, HasCMov]>;
|
||||
def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>,
|
||||
Requires<[HasCMov]>;
|
||||
}
|
||||
|
||||
|
||||
@ -169,7 +169,7 @@ def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
||||
|
||||
def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>;
|
||||
def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>;
|
||||
def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
|
||||
def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP, [SDNPHasChain]>;
|
||||
def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
|
||||
def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
|
||||
|
||||
@ -181,7 +181,7 @@ def X86CmpMaskCCScalar :
|
||||
SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
|
||||
SDTCisVT<3, i8>]>;
|
||||
|
||||
def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
|
||||
def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC, [SDNPHasChain]>;
|
||||
def X86cmpmSAE : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>;
|
||||
def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>;
|
||||
def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>;
|
||||
|
||||
@ -142,6 +142,8 @@ def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
|
||||
def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
|
||||
|
||||
def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
|
||||
def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86CmpTest, [SDNPHasChain]>;
|
||||
def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86CmpTest, [SDNPHasChain]>;
|
||||
def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
|
||||
|
||||
def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
|
||||
@ -375,6 +377,9 @@ class X86VMemOperand<RegisterClass RC, string printMethod,
|
||||
}
|
||||
|
||||
def anymem : X86MemOperand<"printanymem">;
|
||||
def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs),
|
||||
[(X86cmp node:$lhs, node:$rhs),
|
||||
(X86strict_fcmp node:$lhs, node:$rhs)]>;
|
||||
|
||||
// FIXME: Right now we allow any size during parsing, but we might want to
|
||||
// restrict to only unsized memory.
|
||||
|
||||
@ -1874,16 +1874,14 @@ let mayLoad = 1 in
|
||||
}
|
||||
|
||||
let Defs = [EFLAGS] in {
|
||||
defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
|
||||
defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86any_fcmp, f32, f32mem, loadf32,
|
||||
"ucomiss", SSEPackedSingle>, PS, VEX, VEX_LIG, VEX_WIG;
|
||||
defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
|
||||
defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86any_fcmp, f64, f64mem, loadf64,
|
||||
"ucomisd", SSEPackedDouble>, PD, VEX, VEX_LIG, VEX_WIG;
|
||||
let Pattern = []<dag> in {
|
||||
defm VCOMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
|
||||
"comiss", SSEPackedSingle>, PS, VEX, VEX_LIG, VEX_WIG;
|
||||
defm VCOMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
|
||||
"comisd", SSEPackedDouble>, PD, VEX, VEX_LIG, VEX_WIG;
|
||||
}
|
||||
defm VCOMISS : sse12_ord_cmp<0x2F, FR32, X86strict_fcmps, f32, f32mem, loadf32,
|
||||
"comiss", SSEPackedSingle>, PS, VEX, VEX_LIG, VEX_WIG;
|
||||
defm VCOMISD : sse12_ord_cmp<0x2F, FR64, X86strict_fcmps, f64, f64mem, loadf64,
|
||||
"comisd", SSEPackedDouble>, PD, VEX, VEX_LIG, VEX_WIG;
|
||||
|
||||
let isCodeGenOnly = 1 in {
|
||||
defm VUCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
|
||||
@ -1896,17 +1894,14 @@ let Defs = [EFLAGS] in {
|
||||
defm VCOMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem,
|
||||
sse_load_f64, "comisd", SSEPackedDouble>, PD, VEX, VEX_LIG, VEX_WIG;
|
||||
}
|
||||
defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
|
||||
defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86any_fcmp, f32, f32mem, loadf32,
|
||||
"ucomiss", SSEPackedSingle>, PS;
|
||||
defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
|
||||
defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86any_fcmp, f64, f64mem, loadf64,
|
||||
"ucomisd", SSEPackedDouble>, PD;
|
||||
|
||||
let Pattern = []<dag> in {
|
||||
defm COMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
|
||||
"comiss", SSEPackedSingle>, PS;
|
||||
defm COMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
|
||||
"comisd", SSEPackedDouble>, PD;
|
||||
}
|
||||
defm COMISS : sse12_ord_cmp<0x2F, FR32, X86strict_fcmps, f32, f32mem, loadf32,
|
||||
"comiss", SSEPackedSingle>, PS;
|
||||
defm COMISD : sse12_ord_cmp<0x2F, FR64, X86strict_fcmps, f64, f64mem, loadf64,
|
||||
"comisd", SSEPackedDouble>, PD;
|
||||
|
||||
let isCodeGenOnly = 1 in {
|
||||
defm UCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
|
||||
|
||||
3063
test/CodeGen/X86/fp-strict-scalar-cmp.ll
Normal file
3063
test/CodeGen/X86/fp-strict-scalar-cmp.ll
Normal file
File diff suppressed because it is too large
Load Diff
992
test/CodeGen/X86/fp80-strict-scalar-cmp.ll
Normal file
992
test/CodeGen/X86/fp80-strict-scalar-cmp.ll
Normal file
@ -0,0 +1,992 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 | FileCheck %s --check-prefixes=CHECK,X87-32
|
||||
; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -O3 | FileCheck %s --check-prefixes=CHECK,X87-64
|
||||
|
||||
define i32 @test_oeq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_oeq_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: jne .LBB0_3
|
||||
; X87-32-NEXT: # %bb.1:
|
||||
; X87-32-NEXT: jp .LBB0_3
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: .LBB0_3:
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_oeq_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovnel %esi, %eax
|
||||
; X87-64-NEXT: cmovpl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"oeq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ogt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ogt_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: ja .LBB1_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB1_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ogt_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovbel %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ogt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_oge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_oge_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jae .LBB2_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB2_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_oge_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovbl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"oge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_olt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_olt_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: ja .LBB3_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB3_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_olt_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovbel %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"olt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ole_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ole_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jae .LBB4_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB4_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ole_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovbl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ole",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_one_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_one_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jne .LBB5_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB5_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_one_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovel %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"one",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ord_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ord_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jnp .LBB6_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB6_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ord_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovpl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ord",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ueq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ueq_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: je .LBB7_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB7_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ueq_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovnel %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ueq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ugt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ugt_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jb .LBB8_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB8_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ugt_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovael %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ugt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_uge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_uge_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jbe .LBB9_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB9_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_uge_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmoval %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"uge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ult_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ult_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jb .LBB10_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB10_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ult_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovael %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ult",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ule_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ule_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jbe .LBB11_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB11_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ule_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmoval %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ule",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_une_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_une_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: jne .LBB12_3
|
||||
; X87-32-NEXT: # %bb.1:
|
||||
; X87-32-NEXT: jp .LBB12_3
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: .LBB12_3:
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_une_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %esi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovnel %edi, %eax
|
||||
; X87-64-NEXT: cmovpl %edi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"une",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_uno_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_uno_q:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fucompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jp .LBB13_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB13_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_uno_q:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fucompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovnpl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"uno",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_oeq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_oeq_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: jne .LBB14_3
|
||||
; X87-32-NEXT: # %bb.1:
|
||||
; X87-32-NEXT: jp .LBB14_3
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: .LBB14_3:
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_oeq_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovnel %esi, %eax
|
||||
; X87-64-NEXT: cmovpl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"oeq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ogt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ogt_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: ja .LBB15_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB15_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ogt_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovbel %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ogt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_oge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_oge_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jae .LBB16_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB16_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_oge_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovbl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"oge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_olt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_olt_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: ja .LBB17_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB17_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_olt_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovbel %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"olt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ole_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ole_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jae .LBB18_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB18_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ole_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovbl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ole",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_one_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_one_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jne .LBB19_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB19_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_one_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovel %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"one",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ord_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ord_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jnp .LBB20_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB20_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ord_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovpl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ord",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ueq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ueq_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: je .LBB21_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB21_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ueq_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovnel %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ueq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ugt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ugt_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jb .LBB22_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB22_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ugt_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovael %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ugt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_uge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_uge_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jbe .LBB23_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB23_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_uge_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmoval %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"uge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ult_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ult_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jb .LBB24_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB24_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ult_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovael %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ult",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_ule_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_ule_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jbe .LBB25_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB25_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_ule_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmoval %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"ule",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_une_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_une_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: jne .LBB26_3
|
||||
; X87-32-NEXT: # %bb.1:
|
||||
; X87-32-NEXT: jp .LBB26_3
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: .LBB26_3:
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_une_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %esi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovnel %edi, %eax
|
||||
; X87-64-NEXT: cmovpl %edi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"une",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_uno_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
|
||||
; X87-32-LABEL: test_uno_s:
|
||||
; X87-32: # %bb.0:
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
|
||||
; X87-32-NEXT: fcompp
|
||||
; X87-32-NEXT: fnstsw %ax
|
||||
; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; X87-32-NEXT: sahf
|
||||
; X87-32-NEXT: jp .LBB27_1
|
||||
; X87-32-NEXT: # %bb.2:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
; X87-32-NEXT: .LBB27_1:
|
||||
; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
|
||||
; X87-32-NEXT: movl (%eax), %eax
|
||||
; X87-32-NEXT: retl
|
||||
;
|
||||
; X87-64-LABEL: test_uno_s:
|
||||
; X87-64: # %bb.0:
|
||||
; X87-64-NEXT: movl %edi, %eax
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
|
||||
; X87-64-NEXT: fcompi %st(1), %st
|
||||
; X87-64-NEXT: fstp %st(0)
|
||||
; X87-64-NEXT: cmovnpl %esi, %eax
|
||||
; X87-64-NEXT: retq
|
||||
%cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
|
||||
x86_fp80 %f1, x86_fp80 %f2, metadata !"uno",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
attributes #0 = { strictfp }
|
||||
|
||||
declare i1 @llvm.experimental.constrained.fcmp.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
|
||||
declare i1 @llvm.experimental.constrained.fcmps.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
|
||||
1681
test/CodeGen/X86/vec-strict-128-cmp.ll
Normal file
1681
test/CodeGen/X86/vec-strict-128-cmp.ll
Normal file
File diff suppressed because it is too large
Load Diff
1243
test/CodeGen/X86/vec-strict-256-cmp.ll
Normal file
1243
test/CodeGen/X86/vec-strict-256-cmp.ll
Normal file
File diff suppressed because it is too large
Load Diff
961
test/CodeGen/X86/vec-strict-512-cmp.ll
Normal file
961
test/CodeGen/X86/vec-strict-512-cmp.ll
Normal file
@ -0,0 +1,961 @@
|
||||
; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-32
|
||||
; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-64
|
||||
|
||||
define <16 x i32> @test_v16f32_oeq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_oeq_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpeqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_oeq_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpeqps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"oeq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ogt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ogt_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpgt_oqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ogt_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmplt_oqps %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ogt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_oge_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_oge_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpge_oqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_oge_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmple_oqps %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"oge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_olt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_olt_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmplt_oqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_olt_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmplt_oqps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"olt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ole_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ole_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmple_oqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ole_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmple_oqps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ole",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_one_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_one_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpneq_oqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_one_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpneq_oqps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"one",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ord_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ord_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpordps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ord_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpordps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ord",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ueq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ueq_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpeq_uqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ueq_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpeq_uqps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ueq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ugt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ugt_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnle_uqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ugt_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnle_uqps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ugt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_uge_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_uge_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnlt_uqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_uge_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnlt_uqps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"uge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ult_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ult_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnge_uqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ult_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnle_uqps %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ult",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ule_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ule_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpngt_uqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ule_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnlt_uqps %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ule",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_une_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_une_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpneqps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_une_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpneqps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"une",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_uno_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_uno_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpunordps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_uno_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpunordps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"uno",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_oeq_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_oeq_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpeqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_oeq_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpeqpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"oeq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ogt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ogt_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpgt_oqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ogt_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmplt_oqpd %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ogt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_oge_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_oge_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpge_oqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_oge_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmple_oqpd %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"oge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_olt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_olt_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmplt_oqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_olt_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmplt_oqpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"olt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ole_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ole_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmple_oqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ole_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmple_oqpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ole",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_one_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_one_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpneq_oqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_one_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpneq_oqpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"one",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ord_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ord_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpordpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ord_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpordpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ord",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ueq_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ueq_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpeq_uqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ueq_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpeq_uqpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ueq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ugt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ugt_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnle_uqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ugt_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnle_uqpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ugt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_uge_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_uge_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnlt_uqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_uge_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnlt_uqpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"uge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ult_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ult_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnge_uqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ult_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnle_uqpd %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ult",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ule_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ule_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpngt_uqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ule_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnlt_uqpd %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ule",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_une_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_une_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpneqpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_une_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpneqpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"une",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_uno_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_uno_q:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpunordpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_uno_q:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpunordpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"uno",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_oeq_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_oeq_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpeq_osps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_oeq_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpeq_osps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"oeq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ogt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ogt_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpgtps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ogt_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpltps %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ogt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_oge_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_oge_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpgeps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_oge_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpleps %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"oge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_olt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_olt_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpltps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_olt_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpltps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"olt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ole_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ole_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpleps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ole_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpleps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ole",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_one_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_one_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpneq_osps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_one_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpneq_osps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"one",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ord_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ord_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpord_sps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ord_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpord_sps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ord",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ueq_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ueq_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpeq_usps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ueq_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpeq_usps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ueq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ugt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ugt_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnleps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ugt_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnleps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ugt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_uge_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_uge_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnltps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_uge_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnltps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"uge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ult_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ult_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpngeps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ult_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnleps %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ult",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_ule_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_ule_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpngtps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_ule_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnltps %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"ule",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_une_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_une_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpneq_usps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_une_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpneq_usps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"une",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_v16f32_uno_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v16f32_uno_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpunord_sps 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v16f32_uno_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpunord_sps %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
|
||||
<16 x float> %f1, <16 x float> %f2, metadata !"uno",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_oeq_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_oeq_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpeq_ospd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_oeq_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpeq_ospd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"oeq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ogt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ogt_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpgtpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ogt_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpltpd %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ogt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_oge_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_oge_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpgepd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_oge_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmplepd %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"oge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_olt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_olt_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpltpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_olt_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpltpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"olt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ole_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ole_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmplepd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ole_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmplepd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ole",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_one_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_one_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpneq_ospd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_one_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpneq_ospd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"one",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ord_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ord_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpord_spd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ord_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpord_spd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ord",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ueq_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ueq_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpeq_uspd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ueq_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpeq_uspd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ueq",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ugt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ugt_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnlepd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ugt_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnlepd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ugt",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_uge_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_uge_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpnltpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_uge_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnltpd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"uge",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ult_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ult_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpngepd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ult_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnlepd %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ult",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_ule_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_ule_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpngtpd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_ule_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpnltpd %zmm2, %zmm3, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"ule",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_une_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_une_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpneq_uspd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_une_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpneq_uspd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"une",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_v8f64_uno_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
|
||||
; AVX512-32-LABEL: test_v8f64_uno_s:
|
||||
; AVX512-32: # %bb.0:
|
||||
; AVX512-32: vcmpunord_spd 8(%ebp), %zmm2, %k1
|
||||
; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
;
|
||||
; AVX512-64-LABEL: test_v8f64_uno_s:
|
||||
; AVX512-64: # %bb.0:
|
||||
; AVX512-64-NEXT: vcmpunord_spd %zmm3, %zmm2, %k1
|
||||
; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
|
||||
%cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
|
||||
<8 x double> %f1, <8 x double> %f2, metadata !"uno",
|
||||
metadata !"fpexcept.strict") #0
|
||||
%res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
attributes #0 = { strictfp }
|
||||
|
||||
declare <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float>, <16 x float>, metadata, metadata)
|
||||
declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double>, <8 x double>, metadata, metadata)
|
||||
declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float>, <16 x float>, metadata, metadata)
|
||||
declare <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double>, <8 x double>, metadata, metadata)
|
||||
Loading…
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Reference in New Issue
Block a user