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Implement methods that enable expansion of load immediate
macro instruction (li) in the assembler.
We have identified three possible expansions depending on
the size of immediate operand:
1) for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
2) for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
3) for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)
All of the above have been implemented in ths patch.
Contributer: Vladimir Medic
llvm-svn: 165199
This commit is contained in:
Jack Carter
parent
39152df564
commit
a6d222bf00
@ -92,6 +92,12 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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StringRef Mnemonic);
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bool needsExpansion(MCInst &Inst);
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void expandInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst*> &Instructions);
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void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst*> &Instructions);
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bool reportParseError(StringRef ErrorMsg);
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bool parseMemOffset(const MCExpr *&Res);
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@ -296,6 +302,68 @@ public:
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};
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}
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bool MipsAsmParser::needsExpansion(MCInst &Inst) {
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switch(Inst.getOpcode()) {
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case Mips::LoadImm32Reg:
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return true;
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default:
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return false;
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}
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}
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void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst*> &Instructions){
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switch(Inst.getOpcode()) {
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case Mips::LoadImm32Reg:
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return expandLoadImm(Inst, IDLoc, Instructions);
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}
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return;
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}
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void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst*> &Instructions){
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MCInst *tmpInst = new MCInst();
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const MCOperand &ImmOp = Inst.getOperand(1);
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assert(ImmOp.isImm() && "expected imediate operand kind");
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const MCOperand &RegOp = Inst.getOperand(0);
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assert(RegOp.isReg() && "expected register operand kind");
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int ImmValue = ImmOp.getImm();
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tmpInst->setLoc(IDLoc);
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if ( 0 <= ImmValue && ImmValue <= 65535) {
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// for 0 = j = 65535.
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// li d,j => ori d,$zero,j
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tmpInst->setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi);
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tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst->addOperand(
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MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO));
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tmpInst->addOperand(MCOperand::CreateImm(ImmValue));
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Instructions.push_back(tmpInst);
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} else if ( ImmValue < 0 && ImmValue >= -32768) {
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// for -32768 = j < 0.
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// li d,j => addiu d,$zero,j
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tmpInst->setOpcode(Mips::ADDiu); //TODO:no ADDiu64 in td files?
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tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst->addOperand(
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MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO));
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tmpInst->addOperand(MCOperand::CreateImm(ImmValue));
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Instructions.push_back(tmpInst);
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} else {
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// for any other value of j that is representable as a 32-bit integer.
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// li d,j => lui d,hi16(j)
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// ori d,d,lo16(j)
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tmpInst->setOpcode(isMips64() ? Mips::LUi64 : Mips::LUi);
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tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst->addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
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Instructions.push_back(tmpInst);
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tmpInst = new MCInst();
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tmpInst->setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi);
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tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst->addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
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tmpInst->setLoc(IDLoc);
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Instructions.push_back(tmpInst);
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}
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}
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bool MipsAsmParser::
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MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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@ -311,8 +379,17 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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switch (MatchResult) {
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default: break;
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case Match_Success: {
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Inst.setLoc(IDLoc);
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Out.EmitInstruction(Inst);
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if (needsExpansion(Inst)) {
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SmallVector<MCInst*, 4> Instructions;
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expandInstruction(Inst, IDLoc, Instructions);
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for(unsigned i =0; i < Instructions.size(); i++){
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Inst = *(Instructions[i]);
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Out.EmitInstruction(Inst);
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}
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} else {
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Inst.setLoc(IDLoc);
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Out.EmitInstruction(Inst);
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}
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return false;
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}
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case Match_MissingFeature:
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@ -375,7 +452,7 @@ int MipsAsmParser::matchRegisterName(StringRef Name) {
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.Default(-1);
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if (CC != -1) {
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//64 bit register in Mips are following 32 bit definitions.
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// 64 bit register in Mips are following 32 bit definitions.
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if (isMips64())
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CC++;
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return CC;
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@ -385,7 +462,7 @@ int MipsAsmParser::matchRegisterName(StringRef Name) {
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StringRef NumString = Name.substr(1);
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unsigned IntVal;
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if( NumString.getAsInteger(10, IntVal))
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return -1; //not integer
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return -1; // not integer
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if (IntVal > 31)
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return -1;
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@ -397,7 +474,7 @@ int MipsAsmParser::matchRegisterName(StringRef Name) {
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if(isFP64()) {
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return getReg(Mips::FGR64RegClassID, IntVal);
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}
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//only even numbers available as register pairs
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// only even numbers available as register pairs
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if (( IntVal > 31) || (IntVal%2 != 0))
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return -1;
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return getReg(Mips::AFGR64RegClassID, IntVal/2);
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@ -458,7 +535,7 @@ unsigned MipsAsmParser::getReg(int RC,int RegNo) {
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int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic) {
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if (Mnemonic.lower() == "rdhwr") {
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//at the moment only hwreg29 is supported
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// at the moment only hwreg29 is supported
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if (RegNum != 29)
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return -1;
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return Mips::HWR29;
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@ -478,11 +555,11 @@ int MipsAsmParser::tryParseRegister(StringRef Mnemonic) {
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std::string lowerCase = Tok.getString().lower();
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RegNum = matchRegisterName(lowerCase);
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} else if (Tok.is(AsmToken::Integer))
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RegNum = matchRegisterByNumber(static_cast<unsigned> (Tok.getIntVal()),
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RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
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Mnemonic.lower());
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else
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return RegNum; //error
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//64 bit div operations require Mips::ZERO instead of MIPS::ZERO_64
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// 64 bit div operations require Mips::ZERO instead of MIPS::ZERO_64
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if (isMips64() && RegNum == Mips::ZERO_64) {
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if (Mnemonic.find("ddiv") != StringRef::npos)
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RegNum = Mips::ZERO;
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@ -497,11 +574,11 @@ bool MipsAsmParser::
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SMLoc S = Parser.getTok().getLoc();
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int RegNo = -1;
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//FIXME: we should make a more generic method for CCR
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// FIXME: we should make a more generic method for CCR
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if ((Mnemonic == "cfc1" || Mnemonic == "ctc1")
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&& Operands.size() == 2 && Parser.getTok().is(AsmToken::Integer)){
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RegNo = Parser.getTok().getIntVal(); //get the int value
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//at the moment only fcc0 is supported
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RegNo = Parser.getTok().getIntVal(); // get the int value
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// at the moment only fcc0 is supported
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if (RegNo == 0)
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RegNo = Mips::FCC0;
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} else
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@ -517,8 +594,8 @@ bool MipsAsmParser::
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bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
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StringRef Mnemonic) {
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//Check if the current operand has a custom associated parser, if so, try to
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//custom parse the operand, or fallback to the general approach.
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// Check if the current operand has a custom associated parser, if so, try to
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// custom parse the operand, or fallback to the general approach.
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OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
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if (ResTy == MatchOperand_Success)
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return false;
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@ -533,20 +610,20 @@ bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
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Error(Parser.getTok().getLoc(), "unexpected token in operand");
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return true;
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case AsmToken::Dollar: {
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//parse register
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// parse register
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SMLoc S = Parser.getTok().getLoc();
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Parser.Lex(); // Eat dollar token.
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//parse register operand
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if (!tryParseRegisterOperand(Operands,Mnemonic)) {
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// parse register operand
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if (!tryParseRegisterOperand(Operands, Mnemonic)) {
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if (getLexer().is(AsmToken::LParen)) {
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//check if it is indexed addressing operand
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// check if it is indexed addressing operand
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Operands.push_back(MipsOperand::CreateToken("(", S));
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Parser.Lex(); //eat parenthesis
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Parser.Lex(); // eat parenthesis
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if (getLexer().isNot(AsmToken::Dollar))
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return true;
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Parser.Lex(); //eat dollar
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if (tryParseRegisterOperand(Operands,Mnemonic))
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Parser.Lex(); // eat dollar
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if (tryParseRegisterOperand(Operands, Mnemonic))
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return true;
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if (!getLexer().is(AsmToken::RParen))
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@ -558,7 +635,7 @@ bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
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}
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return false;
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}
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//maybe it is a symbol reference
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// maybe it is a symbol reference
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StringRef Identifier;
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if (Parser.ParseIdentifier(Identifier))
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return true;
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@ -590,9 +667,9 @@ bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
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return false;
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}
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case AsmToken::Percent: {
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//it is a symbol reference or constant expression
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// it is a symbol reference or constant expression
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const MCExpr *IdVal;
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SMLoc S = Parser.getTok().getLoc(); //start location of the operand
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SMLoc S = Parser.getTok().getLoc(); // start location of the operand
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if (parseRelocOperand(IdVal))
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return true;
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@ -608,13 +685,13 @@ bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
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bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
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Parser.Lex(); // eat % token
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const AsmToken &Tok = Parser.getTok(); //get next token, operation
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const AsmToken &Tok = Parser.getTok(); // get next token, operation
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if (Tok.isNot(AsmToken::Identifier))
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return true;
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std::string Str = Tok.getIdentifier().str();
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Parser.Lex(); //eat identifier
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Parser.Lex(); // eat identifier
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// now make expression from the rest of the operand
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const MCExpr *IdVal;
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SMLoc EndLoc;
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@ -646,7 +723,7 @@ bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
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// Check the type of the expression
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if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal)) {
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//it's a constant, evaluate lo or hi value
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// it's a constant, evaluate lo or hi value
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int Val = MCE->getValue();
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if (Str == "lo") {
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Val = Val & 0xffff;
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@ -1094,8 +1171,6 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
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}
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if (DirectiveID.getString() == ".set") {
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// ignore this directive for now
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//Parser.EatToEndOfStatement();
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return parseDirectiveSet();
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}
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@ -92,6 +92,14 @@ class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>:
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let Predicates = [HasStandardEncoding];
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}
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// Pseudo-instructions for alternate assembly syntax (never used by codegen).
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// These are aliases that require C++ handling to convert to the target
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// instruction, while InstAliases can be handled directly by tblgen.
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class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
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MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
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let isPseudo = 1;
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let Pattern = [];
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}
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//===----------------------------------------------------------------------===//
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// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
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//===----------------------------------------------------------------------===//
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@ -864,6 +864,10 @@ let usesCustomInserter = 1 in {
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// Instruction definition
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//===----------------------------------------------------------------------===//
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class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> :
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MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
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!strconcat(instr_asm, "\t$rt, $imm32")> ;
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def LoadImm32Reg : LoadImm32<"li",shamt,CPURegs>;
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//===----------------------------------------------------------------------===//
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// MipsI Instructions
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//===----------------------------------------------------------------------===//
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14
test/MC/Mips/mips-expansions.s
Normal file
14
test/MC/Mips/mips-expansions.s
Normal file
@ -0,0 +1,14 @@
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
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# Check that the assembler can handle the documented syntax
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# for macro instructions
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# CHECK: .section __TEXT,__text,regular,pure_instructions
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#------------------------------------------------------------------------------
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# Load immediate instructions
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#------------------------------------------------------------------------------
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# CHECK: ori $5, $zero, 123 # encoding: [0x7b,0x00,0x05,0x34]
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# CHECK: addiu $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24]
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# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
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# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
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li $5,123
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li $6,-2345
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li $7,65538
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