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Go through all kinds of trouble to mark 'blr' as having a predicate operand
that takes a register and condition code. Print these pieces of BLR the right way, even though it is currently set to 'always'. Next up: get the JIT encoding right, then enhance branch folding to produce predicated blr for simple examples. llvm-svn: 31449
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@ -17,13 +17,31 @@
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#include <iosfwd>
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// GCC #defines PPC on Linux but we use it as our namespace name
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#undef PPC
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namespace llvm {
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class PPCTargetMachine;
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class FunctionPassManager;
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class FunctionPass;
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class MachineCodeEmitter;
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class PPCTargetMachine;
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class FunctionPassManager;
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class FunctionPass;
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class MachineCodeEmitter;
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namespace PPC {
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/// Predicate - These are "(BO << 5) | BI" for various predicates.
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enum Predicate {
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PRED_ALWAYS = (20 << 5) | 0,
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PRED_LT = (12 << 5) | 0,
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PRED_LE = ( 4 << 5) | 1,
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PRED_EQ = (12 << 5) | 2,
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PRED_GE = ( 4 << 5) | 0,
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PRED_GT = (12 << 5) | 1,
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PRED_NE = ( 4 << 5) | 2,
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PRED_UN = (12 << 5) | 3,
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PRED_NU = ( 4 << 5) | 3
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};
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}
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FunctionPass *createPPCBranchSelectionPass();
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FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
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FunctionPass *createPPCAsmPrinterPass(std::ostream &OS,
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@ -34,9 +52,6 @@ void addPPCMachOObjectWriterPass(FunctionPassManager &FPM, std::ostream &o,
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PPCTargetMachine &tm);
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} // end namespace llvm;
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// GCC #defines PPC on Linux but we use it as our namespace name
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#undef PPC
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// Defines symbolic names for PowerPC registers. This defines a mapping from
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// register name to register number.
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//
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@ -236,6 +236,9 @@ namespace {
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printOperand(MI, OpNo+1);
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}
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void printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
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const char *Modifier);
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virtual bool runOnMachineFunction(MachineFunction &F) = 0;
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virtual bool doFinalization(Module &M) = 0;
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};
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@ -363,6 +366,33 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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return false;
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}
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void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
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const char *Modifier) {
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assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!");
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unsigned Code = MI->getOperand(OpNo).getImm();
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if (!strcmp(Modifier, "cc")) {
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switch ((PPC::Predicate)Code) {
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case PPC::PRED_ALWAYS: return; // Don't print anything for always.
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case PPC::PRED_LT: O << "lt"; return;
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case PPC::PRED_LE: O << "le"; return;
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case PPC::PRED_EQ: O << "eq"; return;
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case PPC::PRED_GE: O << "ge"; return;
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case PPC::PRED_GT: O << "gt"; return;
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case PPC::PRED_NE: O << "ne"; return;
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case PPC::PRED_UN: O << "un"; return;
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case PPC::PRED_NU: O << "nu"; return;
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}
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} else {
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assert(!strcmp(Modifier, "reg") &&
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"Need to specify 'cc' or 'reg' as predicate op modifier!");
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// Don't print the register for 'always'.
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if (Code == PPC::PRED_ALWAYS) return;
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printOperand(MI, OpNo+1);
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}
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}
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/// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to
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/// the current output stream.
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///
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@ -255,9 +255,11 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
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let MIOperandInfo = (ops i32imm, ptr_rc);
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}
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// PowerPC Predicate operand. 20 = always, CR0 is a dummy reg that doesn't
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// matter.
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def pred : PredicateOperand<(ops imm, CRRC), (ops 20, CR0)>;
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// PowerPC Predicate operand. 640 = ((20<<5)|0) = always, CR0 is a dummy reg
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// that doesn't matter.
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def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 640), CR0)> {
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let PrintMethod = "printPredicateOperand";
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}
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// Define PowerPC specific addressing mode.
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def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
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@ -315,10 +317,13 @@ let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
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let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
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let isReturn = 1 in
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def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
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def BLR : XLForm_2_ext<19, 16, 20, 0, 0,
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(ops pred:$p),
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"b${p:cc}lr ${p:reg}", BrB, [(retflag)]>;
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def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
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}
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
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PPC970_Unit_BRU;
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