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[mips] Add support for mfhc1 and mthc1.
llvm-svn: 188848
This commit is contained in:
Akira Hatanaka
parent
a69a24ff08
commit
a80bdd3ab0
@ -338,6 +338,10 @@ def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>,
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MFC1_FM<0>;
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def MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>,
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MFC1_FM<4>;
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def MFHC1 : MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>,
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MFC1_FM<3>;
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def MTHC1 : MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>,
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MFC1_FM<7>;
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def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1,
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bitconvert>, MFC1_FM<1>;
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def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIFmoveC1,
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@ -526,20 +530,27 @@ def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
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// This pseudo instr gets expanded into 2 mtc1 instrs after register
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// allocation.
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def BuildPairF64 :
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PseudoSE<(outs AFGR64Opnd:$dst),
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(ins GPR32Opnd:$lo, GPR32Opnd:$hi),
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[(set AFGR64Opnd:$dst,
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(MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
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class BuildPairF64Base<RegisterOperand RO> :
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PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
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[(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
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def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>,
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Requires<[IsFP64bit, HasStdEnc]>;
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// This pseudo instr gets expanded into 2 mfc1 instrs after register
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// allocation.
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// if n is 0, lower part of src is extracted.
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// if n is 1, higher part of src is extracted.
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def ExtractElementF64 :
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PseudoSE<(outs GPR32Opnd:$dst), (ins AFGR64Opnd:$src, i32imm:$n),
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[(set GPR32Opnd:$dst,
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(MipsExtractElementF64 AFGR64Opnd:$src, imm:$n))]>;
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class ExtractElementF64Base<RegisterOperand RO> :
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PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
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[(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
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def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
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Requires<[IsFP64bit, HasStdEnc]>;
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//===----------------------------------------------------------------------===//
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// InstAliases.
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@ -263,10 +263,16 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
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break;
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case Mips::BuildPairF64:
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expandBuildPairF64(MBB, MI);
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expandBuildPairF64(MBB, MI, false);
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break;
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case Mips::BuildPairF64_64:
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expandBuildPairF64(MBB, MI, true);
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break;
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case Mips::ExtractElementF64:
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expandExtractElementF64(MBB, MI);
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expandExtractElementF64(MBB, MI, false);
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break;
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case Mips::ExtractElementF64_64:
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expandExtractElementF64(MBB, MI, true);
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break;
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case Mips::PseudoLDC1:
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expandDPLoadStore(MBB, MI, Mips::LDC1, Mips::LWC1);
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@ -419,22 +425,26 @@ void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
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}
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void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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MachineBasicBlock::iterator I,
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bool FP64) const {
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned SrcReg = I->getOperand(1).getReg();
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unsigned N = I->getOperand(2).getImm();
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const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
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DebugLoc dl = I->getDebugLoc();
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assert(N < 2 && "Invalid immediate");
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unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
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unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
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BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
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if (SubIdx == Mips::sub_hi && FP64)
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BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg);
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else
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BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
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}
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void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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MachineBasicBlock::iterator I,
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bool FP64) const {
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
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const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
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@ -445,8 +455,13 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
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// mtc1 Hi, $fp + 1
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BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
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.addReg(LoReg);
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BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
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.addReg(HiReg);
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if (FP64)
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BuildMI(MBB, I, dl, get(Mips::MTHC1), TRI.getSubReg(DstReg, Mips::sub_hi))
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.addReg(HiReg);
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else
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BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
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.addReg(HiReg);
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}
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/// Add 4 to the displacement of operand MO.
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@ -101,9 +101,9 @@ private:
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unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
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void expandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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MachineBasicBlock::iterator I, bool FP64) const;
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void expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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MachineBasicBlock::iterator I, bool FP64) const;
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void expandDPLoadStore(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, unsigned OpcD,
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unsigned OpcS) const;
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@ -1,20 +1,31 @@
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; RUN: llc < %s -march=mipsel | FileCheck %s
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; RUN: llc < %s -march=mips | FileCheck %s
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=FP32
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; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=FP32
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; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64
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; RUN: llc -march=mips -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64
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@a = external global i32
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; CHECK-LABEL: f:
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; FP32: mtc1
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; FP32: mtc1
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; FP64-DAG: mtc1
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; FP64-DAG: mthc1
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define double @f(i32 %a1, double %d) nounwind {
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entry:
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; CHECK: mtc1
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; CHECK: mtc1
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store i32 %a1, i32* @a, align 4
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%add = fadd double %d, 2.000000e+00
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ret double %add
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}
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; CHECK-LABEL: f3:
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; FP32: mfc1
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; FP32: mfc1
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; FP64-DAG: mfc1
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; FP64-DAG: mfhc1
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define void @f3(double %d, i32 %a1) nounwind {
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entry:
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; CHECK: mfc1
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; CHECK: mfc1
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tail call void @f2(i32 %a1, double %d) nounwind
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ret void
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}
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