RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-11 21:45:16 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[AVR] Optimize 16-bit ANDs with '1'

Browse Source 
Summary: Fixes PR 31345

Reviewers: dylanmckay

Subscribers: fhahn, llvm-commits

Differential Revision: https://reviews.llvm.org/D28186

llvm-svn: 290778
This commit is contained in:
Dylan McKay 2016-12-31 01:07:14 +00:00
parent 2266c1322b
commit a840a5bb5c
3 changed files with 57 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/AVR/AVRExpandPseudoInsts.cpp
View File

@ -203,6 +203,10 @@ expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
bool AVRExpandPseudo::
isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const {
// ANDI Rd, 0xff is redundant.
if (Op == AVR::ANDIRdK && ImmVal == 0xff)
return true;
// ORI Rd, 0x0 is redundant.
if (Op == AVR::ORIRdK && ImmVal == 0x0)
return true;

51
test/CodeGen/AVR/PR31345.ll Normal file
View File

@ -0,0 +1,51 @@
; RUN: llc < %s -march=avr | FileCheck %s
; Unit test for: PR 31345
define i16 @and16_reg_imm_0xff00(i16 %a) {
; CHECK-LABEL: and16_reg_imm_0xff00
; CHECK: andi {{r[0-9]+}}, 0
; CHECK-NOT: andi {{r[0-9]+}}, 255
%result = and i16 %a, 65280
ret i16 %result
}
define i16 @and16_reg_imm_0xffb3(i16 %a) {
; CHECK-LABEL: and16_reg_imm_0xffb3
; CHECK: andi {{r[0-9]+}}, 179
; CHECK-NOT: andi {{r[0-9]+}}, 255
%result = and i16 %a, 65459
ret i16 %result
}
define i16 @and16_reg_imm_0x00ff(i16 %a) {
; CHECK-LABEL: and16_reg_imm_0x00ff
; CHECK-NOT: andi {{r[0-9]+}}, 255
; CHECK: andi {{r[0-9]+}}, 0
%result = and i16 %a, 255
ret i16 %result
}
define i16 @and16_reg_imm_0xb3ff(i16 %a) {
; CHECK-LABEL: and16_reg_imm_0xb3ff
; CHECK-NOT: andi {{r[0-9]+}}, 255
; CHECK: andi {{r[0-9]+}}, 179
%result = and i16 %a, 46079
ret i16 %result
}
define i16 @and16_reg_imm_0xffff(i16 %a) {
; CHECK-LABEL: and16_reg_imm_0xffff
; CHECK-NOT: andi {{r[0-9]+}}, 255
; CHECK-NOT: andi {{r[0-9]+}}, 255
%result = and i16 %a, 65535
ret i16 %result
}
define i16 @and16_reg_imm_0xabcd(i16 %a) {
; CHECK-LABEL: and16_reg_imm_0xabcd
; CHECK: andi {{r[0-9]+}}, 205
; CHECK: andi {{r[0-9]+}}, 171
%result = and i16 %a, 43981
ret i16 %result
}

3
test/CodeGen/AVR/and.ll
View File

@ -67,7 +67,8 @@ define i64 @and64_reg_reg(i64 %a, i64 %b) {
define i64 @and64_reg_imm(i64 %a) {
; CHECK-LABEL: and64_reg_imm:
; CHECK: andi r18, 253
; CHECK: andi r19, 255
; Per PR 31345, we optimize away ANDI Rd, 0xff
; CHECK-NOT: andi r19, 255
; CHECK: andi r20, 155
; CHECK: andi r21, 88
; CHECK: andi r22, 76