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[ValueTracking] improve analysis for fdiv with same operands
(The 'nnan' variant of this pattern is already tested to produce '1.0'.) https://alive2.llvm.org/ce/z/D4hPBy define i1 @src(float %x, i32 %y) { %0: %d = fdiv float %x, %x %uge = fcmp uge float %d, 0.000000 ret i1 %uge } => define i1 @tgt(float %x, i32 %y) { %0: ret i1 1 } Transformation seems to be correct!
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@ -3340,14 +3340,15 @@ static bool cannotBeOrderedLessThanZeroImpl(const Value *V,
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case Instruction::UIToFP:
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return true;
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case Instruction::FMul:
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// x*x is always non-negative or a NaN.
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case Instruction::FDiv:
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// X * X is always non-negative or a NaN.
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// X / X is always exactly 1.0 or a NaN.
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if (I->getOperand(0) == I->getOperand(1) &&
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(!SignBitOnly || cast<FPMathOperator>(I)->hasNoNaNs()))
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return true;
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LLVM_FALLTHROUGH;
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case Instruction::FAdd:
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case Instruction::FDiv:
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case Instruction::FRem:
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return cannotBeOrderedLessThanZeroImpl(I->getOperand(0), TLI, SignBitOnly,
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Depth + 1) &&
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@ -205,9 +205,7 @@ define i1 @orderedLessZeroTree(float,float,float,float) {
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define i1 @orderedLessZero_fdiv(float %x) {
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; CHECK-LABEL: @orderedLessZero_fdiv(
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; CHECK-NEXT: [[D:%.*]] = fdiv float [[X:%.*]], [[X]]
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; CHECK-NEXT: [[UGE:%.*]] = fcmp uge float [[D]], 0.000000e+00
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; CHECK-NEXT: ret i1 [[UGE]]
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; CHECK-NEXT: ret i1 true
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;
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%d = fdiv float %x, %x
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%uge = fcmp uge float %d, 0.0
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