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llvm-svn: 150098
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@ -182,7 +182,7 @@ namespace {
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/// invariant. I.e., all virtual register operands are defined outside of
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/// the loop, physical registers aren't accessed (explicitly or implicitly),
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/// and the instruction is hoistable.
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///
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///
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bool IsLoopInvariantInst(MachineInstr &I);
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/// HasAnyPHIUse - Return true if the specified register is used by any
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@ -586,7 +586,7 @@ void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
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MachineBasicBlock *MBB = MI->getParent();
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Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
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// Add register to livein list to all the BBs in the current loop since a
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// Add register to livein list to all the BBs in the current loop since a
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// loop invariant must be kept live throughout the whole loop. This is
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// important to ensure later passes do not scavenge the def register.
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AddToLiveIns(Def);
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@ -600,7 +600,7 @@ void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
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bool MachineLICM::IsGuaranteedToExecute(MachineBasicBlock *BB) {
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if (SpeculationState != SpeculateUnknown)
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return SpeculationState == SpeculateFalse;
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if (BB != CurLoop->getHeader()) {
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// Check loop exiting blocks.
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SmallVector<MachineBasicBlock*, 8> CurrentLoopExitingBlocks;
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@ -758,7 +758,7 @@ MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
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RCCost = TLI->getRepRegClassCostFor(VT);
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}
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}
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/// InitRegPressure - Find all virtual register references that are liveout of
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/// the preheader to initialize the starting "register pressure". Note this
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/// does not count live through (livein but not used) registers.
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@ -842,16 +842,16 @@ void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
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}
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}
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/// isLoadFromGOTOrConstantPool - Return true if this machine instruction
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/// isLoadFromGOTOrConstantPool - Return true if this machine instruction
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/// loads from global offset table or constant pool.
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static bool isLoadFromGOTOrConstantPool(MachineInstr &MI) {
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assert (MI.mayLoad() && "Expected MI that loads!");
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for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
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E = MI.memoperands_end(); I != E; ++I) {
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E = MI.memoperands_end(); I != E; ++I) {
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if (const Value *V = (*I)->getValue()) {
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if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
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if (PSV == PSV->getGOT() || PSV == PSV->getConstantPool())
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return true;
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return true;
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}
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}
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return false;
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@ -872,7 +872,7 @@ bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
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// from constant memory are not safe to speculate all the time, for example
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// indexed load from a jump table.
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// Stores and side effects are already checked by isSafeToMove.
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if (I.mayLoad() && !isLoadFromGOTOrConstantPool(I) &&
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if (I.mayLoad() && !isLoadFromGOTOrConstantPool(I) &&
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!IsGuaranteedToExecute(I.getParent()))
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return false;
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@ -883,7 +883,7 @@ bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
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/// invariant. I.e., all virtual register operands are defined outside of the
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/// loop, physical registers aren't accessed explicitly, and there are no side
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/// effects that aren't captured by the operands or other flags.
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///
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///
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bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
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if (!IsLICMCandidate(I))
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return false;
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@ -1021,7 +1021,7 @@ bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
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bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost) {
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for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
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CI != CE; ++CI) {
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if (CI->second <= 0)
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if (CI->second <= 0)
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continue;
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unsigned RCId = CI->first;
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@ -1102,7 +1102,7 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
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return false;
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} else {
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// Estimate register pressure to determine whether to LICM the instruction.
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// In low register pressure situation, we can be more aggressive about
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// In low register pressure situation, we can be more aggressive about
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// hoisting. Also, favors hoisting long latency instructions even in
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// moderately high pressure situation.
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// FIXME: If there are long latency loop-invariant instructions inside the
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