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[AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.
This is a follow on commit to r[x] where we fix the other direction of copy. For this case, after converting the source from gpr32 -> fpr32, we use a subregister copy, which is essentially what EXTRACT_SUBREG does in SDAG land. https://reviews.llvm.org/D43444 llvm-svn: 325550
This commit is contained in:
Amara Emerson
parent
fc84bda806
commit
a99b25a021
@ -317,12 +317,39 @@ static unsigned selectLoadStoreUIOp(unsigned GenericOpc, unsigned RegBankID,
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return GenericOpc;
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}
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static bool selectFP16CopyFromGPR32(MachineInstr &I, const TargetInstrInfo &TII,
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MachineRegisterInfo &MRI, unsigned SrcReg) {
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// Copies from gpr32 to fpr16 need to use a sub-register copy.
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unsigned CopyReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
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BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::COPY))
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.addDef(CopyReg)
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.addUse(SrcReg);
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unsigned SubRegCopy = MRI.createVirtualRegister(&AArch64::FPR16RegClass);
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BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY))
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.addDef(SubRegCopy)
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.addUse(CopyReg, 0, AArch64::hsub);
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MachineOperand &RegOp = I.getOperand(1);
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RegOp.setReg(SubRegCopy);
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return true;
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}
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static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
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MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) {
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unsigned DstReg = I.getOperand(0).getReg();
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unsigned SrcReg = I.getOperand(1).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
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if (TRI.getRegClass(AArch64::FPR16RegClassID)->contains(DstReg) &&
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!TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
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const RegisterBank &RegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
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const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(
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MRI.getType(SrcReg), RegBank, RBI, /* GetAllRegSet */ true);
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if (SrcRC == &AArch64::GPR32allRegClass)
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return selectFP16CopyFromGPR32(I, TII, MRI, SrcReg);
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}
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assert(I.isCopy() && "Generic operators do not allow physical registers");
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return true;
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}
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@ -330,7 +357,6 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
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const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
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const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
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(void)DstSize;
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unsigned SrcReg = I.getOperand(1).getReg();
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const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
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(void)SrcSize;
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assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) &&
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@ -357,9 +383,7 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
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}
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if (!TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
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const RegClassOrRegBank &RegClassOrBank =
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MRI.getRegClassOrRegBank(SrcReg);
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const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(SrcReg);
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const TargetRegisterClass *SrcRC =
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RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
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const RegisterBank *RB = nullptr;
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@ -378,6 +402,9 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
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.addImm(AArch64::hsub);
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MachineOperand &RegOp = I.getOperand(1);
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RegOp.setReg(PromoteReg);
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} else if (RC == &AArch64::FPR16RegClass &&
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SrcRC == &AArch64::GPR32allRegClass) {
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selectFP16CopyFromGPR32(I, TII, MRI, SrcReg);
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}
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}
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@ -6,18 +6,21 @@
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-arm-none-eabi"
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%struct.struct2 = type { [2 x half] }
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@global_arg0 = common dso_local global %struct.struct2 zeroinitializer, align 2
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; Function Attrs: noinline nounwind optnone
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define dso_local void @c_test([2 x half], [2 x half]* %addr) {
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store [2 x half] %0, [2 x half]* %addr, align 2
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define void @fp16_to_gpr([2 x half], [2 x half]* %addr) {
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ret void
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}
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define void @gpr_to_fp16() {
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ret void
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}
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define void @gpr_to_fp16_physreg() {
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ret void
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}
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...
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---
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name: c_test
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name: fp16_to_gpr
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alignment: 2
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legalized: true
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regBankSelected: true
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@ -40,7 +43,7 @@ body: |
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bb.1 (%ir-block.1):
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liveins: $h0, $h1, $x0
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; CHECK-LABEL: name: c_test
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; CHECK-LABEL: name: fp16_to_gpr
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; CHECK: liveins: $h0, $h1, $x0
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
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@ -67,3 +70,58 @@ body: |
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RET_ReallyLR
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...
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---
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name: gpr_to_fp16
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: fpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $w0
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; CHECK-LABEL: name: gpr_to_fp16
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
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; CHECK: $h0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s16) = G_TRUNC %0(s32)
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%2:fpr(s16) = COPY %1(s16)
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$h0 = COPY %2(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: gpr_to_fp16_physreg
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $w0
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; CHECK-LABEL: name: gpr_to_fp16_physreg
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
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; CHECK: $h0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s16) = G_TRUNC %0(s32)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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@ -97,8 +97,12 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
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; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 15, 30
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; CHECK: $h0 = COPY [[UBFMWri]]
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; CHECK: $h1 = COPY [[UBFMWri1]]
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[UBFMWri]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
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; CHECK: $h0 = COPY [[COPY2]]
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; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
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; CHECK: [[COPY4:%[0-9]+]]:fpr16 = COPY [[COPY3]].hsub
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; CHECK: $h1 = COPY [[COPY4]]
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%0:gpr(s32) = COPY $w0
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%1:gpr(s16) = G_EXTRACT %0, 0
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