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[TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombiner::isAfterLegalizeDAG since that's what it checks. NFC

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The code checks Level == AfterLegalizeDAG which is the fourth and last of the possible DAG combine stages that we have.

There is a Level called AfterLegalVectorOps, but that's the third DAG combine and it doesn't always run.

A function called isAfterLegalVectorOps should imply it returns true in either of the DAG combines that runs after the legalize vector ops stage, but that's not what this function does.

llvm-svn: 326832
This commit is contained in:
Craig Topper 2018-03-06 19:44:52 +00:00
parent 759a2d69ab
commit aa767fb661
4 changed files with 4 additions and 4 deletions
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2
include/llvm/CodeGen/TargetLowering.h
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@ -2798,7 +2798,7 @@ public:
bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
bool isAfterLegalizeVectorOps() const {
bool isAfterLegalizeDAG() const {
return Level == AfterLegalizeDAG;
}
CombineLevel getDAGCombineLevel() { return Level; }

2
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -5904,7 +5904,7 @@ SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
// easier if i8 vectors weren't promoted to i32 vectors, particularly after
// types are legalized. v4i8 -> v4f32 is probably the only case to worry
// about in practice.
if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) {
if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
DCI.AddToWorklist(Cvt.getNode());

2
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -10982,7 +10982,7 @@ SDValue PPCTargetLowering::ConvertSETCCToSubtract(SDNode *N,
// Size of integers being compared has a critical role in the following
// analysis, so we prefer to do this when all types are legal.
if (!DCI.isAfterLegalizeVectorOps())
if (!DCI.isAfterLegalizeDAG())
return SDValue();
// If all users of SETCC extend its value to a legal integer type

2
lib/Target/X86/X86ISelLowering.cpp
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@ -33155,7 +33155,7 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
// Only do this on the last DAG combine as it can interfere with other
// combines.
if (!DCI.isAfterLegalizeVectorOps())
if (!DCI.isAfterLegalizeDAG())
return SDValue();
// Try to improve a sequence of srl (and X, C1), C2 by inverting the order.