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[AMDGPU][MC] Fix for Bug 28211 + LIT tests
- corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
This commit is contained in:
Dmitry Preobrazhensky
parent
0a381d6586
commit
ab371a9d51
@ -203,20 +203,28 @@ class DS_1A <string opName> : DS_Pseudo<opName,
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let has_data1 = 0;
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}
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class DS_1A_GDS <string opName> : DS_Pseudo<opName,
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(outs),
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(ins VGPR_32:$addr),
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"$addr gds"> {
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class DS_GWS <string opName, dag ins, string asmOps>
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: DS_Pseudo<opName, (outs), ins, asmOps> {
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let has_vdst = 0;
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let has_data0 = 0;
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let has_data1 = 0;
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let has_offset = 0;
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let has_offset0 = 0;
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let has_offset1 = 0;
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let has_vdst = 0;
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let has_addr = 0;
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let has_data0 = 0;
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let has_data1 = 0;
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let has_gds = 0;
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let gdsValue = 1;
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let has_gds = 0;
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let gdsValue = 1;
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let AsmMatchConverter = "cvtDSGds";
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}
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class DS_GWS_0D <string opName>
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: DS_GWS<opName,
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(ins offset:$offset, gds:$gds), "$offset gds">;
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class DS_GWS_1D <string opName>
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: DS_GWS<opName,
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(ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
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let has_data0 = 1;
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}
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class DS_VOID <string opName> : DS_Pseudo<opName,
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@ -390,11 +398,11 @@ def DS_WRXCHG2_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64
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def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
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AtomicNoRet<"ds_wrxchg2st64_b64", 1>;
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def DS_GWS_INIT : DS_1A_GDS<"ds_gws_init">;
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def DS_GWS_SEMA_V : DS_1A_GDS<"ds_gws_sema_v">;
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def DS_GWS_SEMA_BR : DS_1A_GDS<"ds_gws_sema_br">;
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def DS_GWS_SEMA_P : DS_1A_GDS<"ds_gws_sema_p">;
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def DS_GWS_BARRIER : DS_1A_GDS<"ds_gws_barrier">;
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def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
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def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
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def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
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def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
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def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
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def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
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def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
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@ -405,7 +413,7 @@ def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
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def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
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def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
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def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
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def DS_AND_SRC2_B32 : DS_1A<"ds_and_src_b32">;
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def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
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def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
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def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
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def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
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@ -448,25 +456,22 @@ def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
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def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
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}
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let SubtargetPredicate = isSICI in {
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def DS_CONSUME : DS_0A_RET<"ds_consume">;
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def DS_APPEND : DS_0A_RET<"ds_append">;
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def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definitions for CI and newer.
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//===----------------------------------------------------------------------===//
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// Remaining instructions:
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// DS_GWS_SEMA_RELEASE_ALL
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// DS_WRAP_RTN_B32
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// DS_CNDXCHG32_RTN_B64
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// DS_CONDXCHG32_RTN_B128
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let SubtargetPredicate = isCIVI in {
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def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">,
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AtomicNoRet<"ds_wrap_f32", 1>;
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def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>;
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def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
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AtomicNoRet<"", 1>;
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def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
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let mayStore = 0 in {
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def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
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@ -678,8 +683,10 @@ def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
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def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
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def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
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// FIXME: this instruction is actually CI/VI
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def DS_WRAP_RTN_F32_si : DS_Real_si<0x34, DS_WRAP_RTN_F32>;
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// These instruction are CI/VI only
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def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
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def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
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def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
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def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
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def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
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@ -820,11 +827,11 @@ def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
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def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
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def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
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def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
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def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>;
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def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
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def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
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def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>;
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def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>;
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def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
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def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
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def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
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def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
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def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
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def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
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def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
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def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
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@ -847,7 +854,7 @@ def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
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def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
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def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
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def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
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def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>;
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def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
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def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
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def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
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def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
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@ -856,6 +863,9 @@ def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
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def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
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def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
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def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
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def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
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def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
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def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
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def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
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def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
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def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
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@ -897,6 +907,8 @@ def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
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def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
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def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
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def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
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def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
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def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
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def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
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def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
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def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
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@ -113,7 +113,7 @@ void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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uint16_t Imm = MI->getOperand(OpNo).getImm();
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if (Imm != 0) {
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O << " offset:";
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O << ((OpNo == 0)? "offset:" : " offset:");
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printU16ImmDecOperand(MI, OpNo, O);
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}
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}
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@ -140,24 +140,32 @@ ds_max_f32 v2, v4
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// VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
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ds_gws_init v2 gds
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// SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00]
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// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
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// SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x00,0x02,0x00,0x00]
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// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
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ds_gws_sema_v v2 gds
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// SICI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x00]
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// VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00]
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ds_gws_init v3 offset:12345 gds
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// SICI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x66,0xd8,0x00,0x03,0x00,0x00]
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// VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00]
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ds_gws_sema_v gds
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// SICI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
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// VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
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ds_gws_sema_v offset:257 gds
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// SICI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x6a,0xd8,0x00,0x00,0x00,0x00]
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// VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00]
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ds_gws_sema_br v2 gds
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// SICI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x00]
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// VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00]
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// SICI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x00,0x02,0x00,0x00]
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// VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00]
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ds_gws_sema_p v2 gds
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// SICI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x72,0xd8,0x02,0x00,0x00,0x00]
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// VI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x39,0xd8,0x02,0x00,0x00,0x00]
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ds_gws_sema_p gds
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// SICI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
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// VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
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ds_gws_barrier v2 gds
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// SICI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x02,0x00,0x00,0x00]
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// VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd8,0x02,0x00,0x00,0x00]
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// SICI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x00,0x02,0x00,0x00]
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// VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00]
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ds_write_b8 v2, v4
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// SICI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x04,0x00,0x00]
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@ -284,17 +292,17 @@ ds_read_u16 v8, v2
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// VI: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x00,0x00,0x08]
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//ds_consume v8
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// FIXMESICI: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08]
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// FIXMEVI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd8,0x00,0x00,0x00,0x08]
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ds_consume v8
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// SICI: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08]
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// VI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x08]
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//ds_append v8
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// FIXMESICI: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08]
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// FIXMEVI: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x00,0x00,0x08]
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ds_append v8
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// SICI: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08]
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// VI: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x08]
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//ds_ordered_count v8, v2 gds
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// FIXMESICI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08]
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// FIXMEVI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd8,0x02,0x00,0x00,0x08]
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ds_ordered_count v8, v2 gds
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// SICI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08]
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// VI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd9,0x02,0x00,0x00,0x08]
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ds_add_u64 v2, v[4:5]
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// SICI: ds_add_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x00,0xd9,0x02,0x04,0x00,0x00]
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@ -11,7 +11,7 @@ s_mov_b32 s0, global
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|
||||
// Use a token with the same name as a global
|
||||
ds_gws_init v2 gds
|
||||
// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
|
||||
// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
|
||||
|
||||
// Use a global with the same name as a token
|
||||
s_mov_b32 s0, gds
|
||||
|
||||
@ -456,19 +456,25 @@ ds_max_f32 v1, v2 offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x00]
|
||||
|
||||
ds_gws_init v1 gds
|
||||
// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x00,0x00,0x00]
|
||||
// CHECK: [0x00,0x00,0x66,0xd8,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_gws_sema_v v1 gds
|
||||
// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x00,0x00,0x00]
|
||||
ds_gws_sema_v gds
|
||||
// CHECK: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_gws_sema_br v1 gds
|
||||
// CHECK: [0x00,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00]
|
||||
// CHECK: [0x00,0x00,0x6e,0xd8,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_gws_sema_p v1 gds
|
||||
// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x00]
|
||||
ds_gws_sema_p gds
|
||||
// CHECK: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_gws_barrier v1 gds
|
||||
// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x00]
|
||||
// CHECK: [0x00,0x00,0x76,0xd8,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_gws_sema_release_all offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_gws_sema_release_all gds
|
||||
// CHECK: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_write_b8 v1, v2 offset:65535
|
||||
// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x02,0x00,0x00]
|
||||
@ -2660,6 +2666,24 @@ ds_max_src2_f64 v1 offset:4
|
||||
ds_max_src2_f64 v1 offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x4e,0xdb,0x01,0x00,0x00,0x00]
|
||||
|
||||
ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
|
||||
// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
|
||||
|
||||
ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x03,0xff]
|
||||
|
||||
ds_wrap_rtn_b32 v255, v1, v2, v3
|
||||
// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0xff]
|
||||
|
||||
ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
|
||||
// CHECK: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
|
||||
|
||||
ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] gds
|
||||
// CHECK: [0x00,0x00,0xfa,0xd9,0x01,0x02,0x00,0x05]
|
||||
|
||||
ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
|
||||
// CHECK: [0xff,0xff,0xf8,0xd9,0x01,0xfe,0x00,0x05]
|
||||
|
||||
exp mrt0, v0, v0, v0, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
|
||||
|
||||
|
||||
@ -2678,6 +2678,90 @@ ds_max_src2_f64 v1 offset:4
|
||||
ds_max_src2_f64 v1 offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0xa7,0xd9,0x01,0x00,0x00,0x00]
|
||||
|
||||
ds_and_src2_b32 v1
|
||||
// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
|
||||
|
||||
ds_and_src2_b32 v1 gds
|
||||
// CHECK: [0x00,0x00,0x13,0xd9,0x01,0x00,0x00,0x00]
|
||||
|
||||
ds_and_src2_b32 v255 offset:65535
|
||||
// CHECK: [0xff,0xff,0x12,0xd9,0xff,0x00,0x00,0x00]
|
||||
|
||||
ds_append v5
|
||||
// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
|
||||
|
||||
ds_append v5 gds
|
||||
// CHECK: [0x00,0x00,0x7d,0xd9,0x00,0x00,0x00,0x05]
|
||||
|
||||
ds_append v255 offset:65535
|
||||
// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0xff]
|
||||
|
||||
ds_consume v5
|
||||
// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
|
||||
|
||||
ds_consume v5 gds
|
||||
// CHECK: [0x00,0x00,0x7b,0xd9,0x00,0x00,0x00,0x05]
|
||||
|
||||
ds_consume v255 offset:65535
|
||||
// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0xff]
|
||||
|
||||
ds_ordered_count v5, v1 gds
|
||||
// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
|
||||
|
||||
ds_ordered_count v5, v255 offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x7f,0xd9,0xff,0x00,0x00,0x05]
|
||||
|
||||
ds_ordered_count v5, v255 gds
|
||||
// CHECK: [0x00,0x00,0x7f,0xd9,0xff,0x00,0x00,0x05]
|
||||
|
||||
ds_gws_barrier v1 gds
|
||||
// CHECK: [0x00,0x00,0x3b,0xd9,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_gws_barrier v255 offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x3b,0xd9,0x00,0xff,0x00,0x00]
|
||||
|
||||
ds_gws_init v1 gds
|
||||
// CHECK: [0x00,0x00,0x33,0xd9,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_gws_init v255 offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x33,0xd9,0x00,0xff,0x00,0x00]
|
||||
|
||||
ds_gws_sema_br v1 gds
|
||||
// CHECK: [0x00,0x00,0x37,0xd9,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_gws_sema_br v255 offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x37,0xd9,0x00,0xff,0x00,0x00]
|
||||
|
||||
ds_gws_sema_p offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_gws_sema_p gds
|
||||
// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_gws_sema_release_all offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_gws_sema_release_all gds
|
||||
// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_gws_sema_v offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_gws_sema_v gds
|
||||
// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
|
||||
|
||||
ds_wrap_rtn_b32 v5, v255, v2, v3 gds
|
||||
// CHECK: [0x00,0x00,0x69,0xd8,0xff,0x02,0x03,0x05]
|
||||
|
||||
ds_wrap_rtn_b32 v5, v255, v2, v255 offset:65535
|
||||
// CHECK: [0xff,0xff,0x68,0xd8,0xff,0x02,0xff,0x05]
|
||||
|
||||
ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535 gds
|
||||
// CHECK: [0xff,0xff,0xfd,0xd8,0x01,0xfe,0x00,0x05]
|
||||
|
||||
ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255]
|
||||
// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0xfe,0x00,0x05]
|
||||
|
||||
exp mrt0, v0, v0, v0, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
|
||||
@ -81,20 +81,26 @@
|
||||
# VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
|
||||
0x00 0x00 0x26 0xd8 0x02 0x04 0x00 0x00
|
||||
|
||||
# VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
|
||||
0x00 0x00 0x33 0xd8 0x02 0x00 0x00 0x00
|
||||
# VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
|
||||
0x00 0x00 0x33 0xd9 0x00 0x02 0x00,0x00
|
||||
|
||||
# VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00]
|
||||
0x00 0x00 0x35 0xd8 0x02 0x00 0x00 0x00
|
||||
# VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00]
|
||||
0x39 0x30 0x33 0xd9 0x00 0x03 0x00 0x00
|
||||
|
||||
# VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00]
|
||||
0x00 0x00 0x37 0xd8 0x02 0x00 0x00 0x00
|
||||
# VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
|
||||
0x00 0x00 0x35 0xd9 0x00 0x00 0x00 0x00
|
||||
|
||||
# VI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x39,0xd8,0x02,0x00,0x00,0x00]
|
||||
0x00 0x00 0x39 0xd8 0x02 0x00 0x00 0x00
|
||||
# VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00]
|
||||
0x01 0x01 0x35 0xd9 0x00 0x00 0x00 0x00
|
||||
|
||||
# VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd8,0x02,0x00,0x00,0x00]
|
||||
0x00 0x00 0x3b 0xd8 0x02 0x00 0x00 0x00
|
||||
# VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00]
|
||||
0x00 0x00 0x37 0xd9 0x00 0x02 0x00 0x00
|
||||
|
||||
# VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
|
||||
0x00 0x00 0x39 0xd9 0x00 0x00 0x00 0x00
|
||||
|
||||
# VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00]
|
||||
0x00 0x00 0x3b 0xd9 0x00 0x02 0x00 0x00
|
||||
|
||||
# VI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x00,0x00]
|
||||
0x00 0x00 0x3c 0xd8 0x02 0x04 0x00 0x00
|
||||
|
||||
Loading…
Reference in New Issue
Block a user