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Enable support for vector sext and trunc:
Limit the folding of any_ext and sext into the load operation to scalars. Limit the active-bits trunc optimization to scalars. Document vector trunc and vector sext in LangRef. Similar to commit 126080 (for enabling zext). llvm-svn: 126424
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Nadav Rotem
parent
3a1fd70006
commit
ab7cf630f4
@ -4575,12 +4575,12 @@ entry:
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type <tt>ty2</tt>.</p>
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<h5>Arguments:</h5>
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<p>The '<tt>trunc</tt>' instruction takes a <tt>value</tt> to trunc, which must
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be an <a href="#t_integer">integer</a> type, and a type that specifies the
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size and type of the result, which must be
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an <a href="#t_integer">integer</a> type. The bit size of <tt>value</tt> must
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be larger than the bit size of <tt>ty2</tt>. Equal sized types are not
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allowed.</p>
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<p>The '<tt>trunc</tt>' instruction takes a value to trunc, and a type to trunc it to.
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Both types must be of <a href="#t_integer">integer</a> types, or vectors
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of the same number of integers.
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The bit size of the <tt>value</tt> must be larger than
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the bit size of the destination type, <tt>ty2</tt>.
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Equal sized types are not allowed.</p>
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<h5>Semantics:</h5>
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<p>The '<tt>trunc</tt>' instruction truncates the high order bits
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@ -4590,9 +4590,10 @@ entry:
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<h5>Example:</h5>
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<pre>
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%X = trunc i32 257 to i8 <i>; yields i8:1</i>
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%Y = trunc i32 123 to i1 <i>; yields i1:true</i>
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%Z = trunc i32 122 to i1 <i>; yields i1:false</i>
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%X = trunc i32 257 to i8 <i>; yields i8:1</i>
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%Y = trunc i32 123 to i1 <i>; yields i1:true</i>
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%Z = trunc i32 122 to i1 <i>; yields i1:false</i>
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%W = trunc <2 x i16> <i16 8, i16 7> to <2 x i8> <i>; yields <i8 8, i8 7></i>
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</pre>
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</div>
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@ -4651,10 +4652,11 @@ entry:
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<p>The '<tt>sext</tt>' sign extends <tt>value</tt> to the type <tt>ty2</tt>.</p>
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<h5>Arguments:</h5>
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<p>The '<tt>sext</tt>' instruction takes a value to cast, which must be of
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<a href="#t_integer">integer</a> type, and a type to cast it to, which must
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also be of <a href="#t_integer">integer</a> type. The bit size of the
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<tt>value</tt> must be smaller than the bit size of the destination type,
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<p>The '<tt>sext</tt>' instruction takes a value to cast, and a type to cast it to.
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Both types must be of <a href="#t_integer">integer</a> types, or vectors
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of the same number of integers.
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The bit size of the <tt>value</tt> must be smaller than
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the bit size of the destination type,
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<tt>ty2</tt>.</p>
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<h5>Semantics:</h5>
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@ -4668,6 +4670,7 @@ entry:
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<pre>
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%X = sext i8 -1 to i16 <i>; yields i16 :65535</i>
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%Y = sext i1 true to i32 <i>; yields i32:-1</i>
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%Z = sext <2 x i16> <i16 8, i16 7> to <2 x i32> <i>; yields <i32 8, i32 7></i>
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</pre>
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</div>
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@ -3685,7 +3685,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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}
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// fold (sext (load x)) -> (sext (truncate (sextload x)))
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if (ISD::isNON_EXTLoad(N0.getNode()) &&
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// None of the supported targets knows how to perform load and sign extend
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// in one instruction. We only perform this transformation on scalars.
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if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
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((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
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TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
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bool DoXform = true;
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@ -4096,7 +4098,9 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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}
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// fold (aext (load x)) -> (aext (truncate (extload x)))
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if (ISD::isNON_EXTLoad(N0.getNode()) &&
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// None of the supported targets knows how to perform load and any_ext
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// in one instruction. We only perform this transformation on scalars.
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if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
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((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
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TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
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bool DoXform = true;
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@ -4506,14 +4510,17 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
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}
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// See if we can simplify the input to this truncate through knowledge that
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// only the low bits are being used. For example "trunc (or (shl x, 8), y)"
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// -> trunc y
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SDValue Shorter =
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GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
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VT.getSizeInBits()));
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if (Shorter.getNode())
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return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
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// only the low bits are being used.
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// For example "trunc (or (shl x, 8), y)" // -> trunc y
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// Currenly we only perform this optimization on scalars because vectors
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// may have different active low bits.
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if (!VT.isVector()) {
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SDValue Shorter =
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GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
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VT.getSizeInBits()));
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if (Shorter.getNode())
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return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
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}
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// fold (truncate (load x)) -> (smaller load x)
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// fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
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if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
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77
test/CodeGen/X86/vec_anyext.ll
Normal file
77
test/CodeGen/X86/vec_anyext.ll
Normal file
@ -0,0 +1,77 @@
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; RUN: llc < %s -march=x86-64
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; PR 9267
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define<4 x i16> @func_16_32() {
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%F = load <4 x i32>* undef
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%G = trunc <4 x i32> %F to <4 x i16>
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%H = load <4 x i32>* undef
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%Y = trunc <4 x i32> %H to <4 x i16>
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%T = add <4 x i16> %Y, %G
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store <4 x i16>%T , <4 x i16>* undef
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ret <4 x i16> %T
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}
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define<4 x i16> @func_16_64() {
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%F = load <4 x i64>* undef
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%G = trunc <4 x i64> %F to <4 x i16>
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%H = load <4 x i64>* undef
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%Y = trunc <4 x i64> %H to <4 x i16>
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%T = xor <4 x i16> %Y, %G
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store <4 x i16>%T , <4 x i16>* undef
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ret <4 x i16> %T
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}
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define<4 x i32> @func_32_64() {
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%F = load <4 x i64>* undef
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%G = trunc <4 x i64> %F to <4 x i32>
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%H = load <4 x i64>* undef
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%Y = trunc <4 x i64> %H to <4 x i32>
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%T = or <4 x i32> %Y, %G
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ret <4 x i32> %T
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}
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define<4 x i8> @func_8_16() {
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%F = load <4 x i16>* undef
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%G = trunc <4 x i16> %F to <4 x i8>
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%H = load <4 x i16>* undef
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%Y = trunc <4 x i16> %H to <4 x i8>
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%T = add <4 x i8> %Y, %G
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ret <4 x i8> %T
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}
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define<4 x i8> @func_8_32() {
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%F = load <4 x i32>* undef
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%G = trunc <4 x i32> %F to <4 x i8>
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%H = load <4 x i32>* undef
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%Y = trunc <4 x i32> %H to <4 x i8>
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%T = sub <4 x i8> %Y, %G
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ret <4 x i8> %T
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}
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define<4 x i8> @func_8_64() {
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%F = load <4 x i64>* undef
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%G = trunc <4 x i64> %F to <4 x i8>
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%H = load <4 x i64>* undef
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%Y = trunc <4 x i64> %H to <4 x i8>
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%T = add <4 x i8> %Y, %G
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ret <4 x i8> %T
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}
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define<4 x i16> @const_16_32() {
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%G = trunc <4 x i32> <i32 0, i32 3, i32 8, i32 7> to <4 x i16>
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ret <4 x i16> %G
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}
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define<4 x i16> @const_16_64() {
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%G = trunc <4 x i64> <i64 0, i64 3, i64 8, i64 7> to <4 x i16>
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ret <4 x i16> %G
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}
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define void @bugOnTruncBitwidthReduce() nounwind {
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meh:
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%0 = xor <4 x i64> zeroinitializer, zeroinitializer
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%1 = trunc <4 x i64> %0 to <4 x i32>
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%2 = lshr <4 x i32> %1, <i32 18, i32 18, i32 18, i32 18>
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%3 = xor <4 x i32> %2, %1
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ret void
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}
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69
test/CodeGen/X86/vec_sext.ll
Normal file
69
test/CodeGen/X86/vec_sext.ll
Normal file
@ -0,0 +1,69 @@
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; RUN: llc < %s -march=x86-64
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; PR 9267
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define<4 x i32> @func_16_32() {
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%F = load <4 x i16>* undef
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%G = sext <4 x i16> %F to <4 x i32>
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%H = load <4 x i16>* undef
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%Y = sext <4 x i16> %H to <4 x i32>
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%T = add <4 x i32> %Y, %G
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store <4 x i32>%T , <4 x i32>* undef
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ret <4 x i32> %T
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}
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define<4 x i64> @func_16_64() {
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%F = load <4 x i16>* undef
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%G = sext <4 x i16> %F to <4 x i64>
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%H = load <4 x i16>* undef
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%Y = sext <4 x i16> %H to <4 x i64>
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%T = xor <4 x i64> %Y, %G
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store <4 x i64>%T , <4 x i64>* undef
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ret <4 x i64> %T
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}
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define<4 x i64> @func_32_64() {
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%F = load <4 x i32>* undef
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%G = sext <4 x i32> %F to <4 x i64>
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%H = load <4 x i32>* undef
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%Y = sext <4 x i32> %H to <4 x i64>
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%T = or <4 x i64> %Y, %G
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ret <4 x i64> %T
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}
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define<4 x i16> @func_8_16() {
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%F = load <4 x i8>* undef
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%G = sext <4 x i8> %F to <4 x i16>
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%H = load <4 x i8>* undef
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%Y = sext <4 x i8> %H to <4 x i16>
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%T = add <4 x i16> %Y, %G
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ret <4 x i16> %T
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}
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define<4 x i32> @func_8_32() {
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%F = load <4 x i8>* undef
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%G = sext <4 x i8> %F to <4 x i32>
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%H = load <4 x i8>* undef
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%Y = sext <4 x i8> %H to <4 x i32>
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%T = sub <4 x i32> %Y, %G
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ret <4 x i32> %T
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}
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define<4 x i64> @func_8_64() {
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%F = load <4 x i8>* undef
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%G = sext <4 x i8> %F to <4 x i64>
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%H = load <4 x i8>* undef
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%Y = sext <4 x i8> %H to <4 x i64>
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%T = add <4 x i64> %Y, %G
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ret <4 x i64> %T
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}
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define<4 x i32> @const_16_32() {
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%G = sext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i32>
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ret <4 x i32> %G
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}
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define<4 x i64> @const_16_64() {
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%G = sext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i64>
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ret <4 x i64> %G
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}
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