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Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
This commit is contained in:
Evan Cheng
parent
0ab209fa54
commit
abcf3842bb
@ -586,8 +586,9 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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CurDAG->getTargetConstant(0, MVT::i32));
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else {
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SDOperand Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 4);
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
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CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
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}
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}
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case ISD::ADD: {
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@ -619,10 +620,9 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
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SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
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CurDAG->getTargetConstant(ShImm, MVT::i32),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32)
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};
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return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 6);
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
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CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
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}
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if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
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SDOperand V = Op.getOperand(0);
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@ -631,8 +631,8 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
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CurDAG->getTargetConstant(ShImm, MVT::i32),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
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};
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return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 6);
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CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
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}
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}
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break;
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@ -645,15 +645,17 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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AddToISelQueue(Op.getOperand(0));
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AddToISelQueue(Op.getOperand(1));
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SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 4);
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
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CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
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}
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case ARMISD::MULHILOS: {
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AddToISelQueue(Op.getOperand(0));
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AddToISelQueue(Op.getOperand(1));
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SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 4);
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
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CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
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}
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case ISD::LOAD: {
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LoadSDNode *LD = cast<LoadSDNode>(Op);
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@ -214,15 +214,18 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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// add more than 1 instruction. Abandon!
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return NULL;
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UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
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.addReg(BaseReg).addImm(SOImmVal).addImm(Pred);
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.addReg(BaseReg).addImm(SOImmVal)
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.addImm(Pred).addReg(0).addReg(0);
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} else if (Amt != 0) {
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ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
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unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
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.addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc).addImm(Pred);
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.addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
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.addImm(Pred).addReg(0).addReg(0);
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} else
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
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.addReg(BaseReg).addReg(OffReg).addImm(Pred);
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.addReg(BaseReg).addReg(OffReg)
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.addImm(Pred).addReg(0).addReg(0);
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break;
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}
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case ARMII::AddrMode3 : {
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@ -231,10 +234,12 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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if (OffReg == 0)
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// Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
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UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
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.addReg(BaseReg).addImm(Amt).addImm(Pred);
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.addReg(BaseReg).addImm(Amt)
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.addImm(Pred).addReg(0).addReg(0);
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else
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
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.addReg(BaseReg).addReg(OffReg).addImm(Pred);
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.addReg(BaseReg).addReg(OffReg)
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.addImm(Pred).addReg(0).addReg(0);
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break;
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}
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}
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@ -495,6 +500,25 @@ ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
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}
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}
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bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
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if (!TID->ImplicitDefs && (TID->Flags & M_HAS_OPTIONAL_DEF) == 0)
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return false;
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bool Found = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == ARM::CPSR) {
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Pred.push_back(MO);
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Found = true;
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}
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}
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return Found;
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}
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/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
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static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
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unsigned JTI) DISABLE_INLINE;
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@ -113,6 +113,9 @@ public:
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virtual
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bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
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const std::vector<MachineOperand> &Pred1) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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};
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// Utility routines
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@ -380,10 +380,25 @@ class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
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list<Predicate> Predicates = [IsARM];
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}
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// Same as I except it can optionally modify CPSR.
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class sI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
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string opc, string asm, string cstr, list<dag> pattern>
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// FIXME: Set all opcodes to 0 for now.
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: InstARM<0, am, sz, im, cstr> {
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let OperandList = !con(oprnds, (ops pred:$p, cc_out:$s));
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let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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class AI<dag ops, string opc, string asm, list<dag> pattern>
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: I<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
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class AsI<dag ops, string opc, string asm, list<dag> pattern>
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: sI<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
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class AI1<dag ops, string opc, string asm, list<dag> pattern>
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: I<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
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class AsI1<dag ops, string opc, string asm, list<dag> pattern>
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: sI<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
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class AI2<dag ops, string opc, string asm, list<dag> pattern>
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: I<ops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
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class AI3<dag ops, string opc, string asm, list<dag> pattern>
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@ -412,21 +427,21 @@ class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
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/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
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/// binop that produces a value.
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multiclass AI1_bin_irs<string opc, PatFrag opnode> {
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def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
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multiclass AsI1_bin_irs<string opc, PatFrag opnode> {
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def ri : AsI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
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opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
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def rr : AsI1<(ops GPR:$dst, GPR:$a, GPR:$b),
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opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
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def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
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def rs : AsI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
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opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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}
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/// AI1_bin_s_irs - Similar to AI1_bin_irs except it sets the 's' bit so the
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/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
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/// instruction modifies the CSPR register.
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multiclass AI1_bin_s_irs<string opc, PatFrag opnode> {
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multiclass ASI1_bin_s_irs<string opc, PatFrag opnode> {
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def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
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opc, "s $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>;
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@ -439,7 +454,7 @@ multiclass AI1_bin_s_irs<string opc, PatFrag opnode> {
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}
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/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
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/// patterns. Similar to AI1_bin_irs except the instruction does not produce
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/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
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/// a explicit result, only implicitly set CPSR.
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multiclass AI1_cmp_irs<string opc, PatFrag opnode> {
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def ri : AI1<(ops GPR:$a, so_imm:$b),
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@ -453,30 +468,6 @@ multiclass AI1_cmp_irs<string opc, PatFrag opnode> {
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[(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>;
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}
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/// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop.
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multiclass AI1_bin_is<string opc, PatFrag opnode> {
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def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
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opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
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opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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}
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/// AI1_unary_irs - Defines a set of (op {so_imm|r|so_reg}) patterns for unary
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/// ops.
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multiclass AI1_unary_irs<string opc, PatFrag opnode> {
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def i : AI1<(ops GPR:$dst, so_imm:$a),
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opc, " $dst, $a",
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[(set GPR:$dst, (opnode so_imm:$a))]>;
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def r : AI1<(ops GPR:$dst, GPR:$a),
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opc, " $dst, $a",
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[(set GPR:$dst, (opnode GPR:$a))]>;
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def s : AI1<(ops GPR:$dst, so_reg:$a),
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opc, " $dst, $a",
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[(set GPR:$dst, (opnode so_reg:$a))]>;
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}
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/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
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/// register and one whose operand is a register rotated by 8/16/24.
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multiclass AI_unary_rrot<string opc, PatFrag opnode> {
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@ -536,17 +527,17 @@ class JTI1<dag ops, string asm, list<dag> pattern>
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class JTI2<dag ops, string asm, list<dag> pattern>
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: XI<ops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
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/// AXI1_bin_c_irs - Same as AI1_bin_irs but without the predicate operand and
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/// setting carry bit.
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multiclass AXI1_bin_c_irs<string opc, PatFrag opnode> {
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def ri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
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!strconcat(opc, " $dst, $a, $b"),
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/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
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/// setting carry bit. But it can optionally set CPSR.
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multiclass AsXI1_bin_c_irs<string opc, PatFrag opnode> {
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def ri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b, cc_out:$s),
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!strconcat(opc, "${s} $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>;
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def rr : AXI1<(ops GPR:$dst, GPR:$a, GPR:$b),
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!strconcat(opc, " $dst, $a, $b"),
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def rr : AXI1<(ops GPR:$dst, GPR:$a, GPR:$b, cc_out:$s),
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!strconcat(opc, "${s} $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>;
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def rs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
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!strconcat(opc, " $dst, $a, $b"),
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def rs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b, cc_out:$s),
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!strconcat(opc, "${s} $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>;
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}
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@ -649,7 +640,7 @@ let isLoad = 1, isReturn = 1, isTerminator = 1 in
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"ldm${p}${addr:submode} $addr, $dst1",
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[]>;
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let isCall = 1, noResults = 1, clobbersPred = 1,
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let isCall = 1, noResults = 1,
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Defs = [R0, R1, R2, R3, R12, LR,
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D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
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def BL : AXI<(ops i32imm:$func, variable_ops),
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@ -697,7 +688,7 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in {
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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// a two-value operand where a dag node expects two operands. :(
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def Bcc : AI<(ops brtarget:$dst), "b", " $dst",
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[/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>;
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[/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>;
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}
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//===----------------------------------------------------------------------===//
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@ -840,29 +831,28 @@ def STM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
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// Move Instructions.
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//
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def MOVr : AI1<(ops GPR:$dst, GPR:$src),
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"mov", " $dst, $src", []>;
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def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
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"mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
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def MOVr : AsI1<(ops GPR:$dst, GPR:$src),
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"mov", " $dst, $src", []>;
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def MOVs : AsI1<(ops GPR:$dst, so_reg:$src),
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"mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
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let isReMaterializable = 1 in
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def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
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"mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
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def MOVi : AsI1<(ops GPR:$dst, so_imm:$src),
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"mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
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def MOVrx : AsI1<(ops GPR:$dst, GPR:$src),
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"mov", " $dst, $src, rrx",
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[(set GPR:$dst, (ARMrrx GPR:$src))]>;
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// These aren't really mov instructions, but we have to define them this way
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// due to flag operands.
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let clobbersPred = 1 in {
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def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
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"mov", "s $dst, $src, lsr #1",
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[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>;
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def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
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"mov", "s $dst, $src, asr #1",
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[(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>;
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}
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def MOVrx : AI1<(ops GPR:$dst, GPR:$src),
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"mov", " $dst, $src, rrx",
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[(set GPR:$dst, (ARMrrx GPR:$src))]>;
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//===----------------------------------------------------------------------===//
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// Extend Instructions.
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@ -907,38 +897,40 @@ defm UXTAH : AI_bin_rrot<"uxtah",
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// Arithmetic Instructions.
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//
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defm ADD : AI1_bin_irs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
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defm SUB : AI1_bin_irs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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defm ADD : AsI1_bin_irs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
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defm SUB : AsI1_bin_irs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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// ADD and SUB with 's' bit set.
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let clobbersPred = 1 in {
|
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defm ADDS : AI1_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
|
||||
defm SUBS : AI1_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
||||
}
|
||||
defm ADDS : ASI1_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
|
||||
defm SUBS : ASI1_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
||||
|
||||
// FIXME: Do not allow ADC / SBC to be predicated for now.
|
||||
defm ADC : AXI1_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
|
||||
defm SBC : AXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
|
||||
defm ADC : AsXI1_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
|
||||
defm SBC : AsXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
|
||||
|
||||
// These don't define reg/reg forms, because they are handled above.
|
||||
defm RSB : AI1_bin_is <"rsb", BinOpFrag<(sub node:$RHS, node:$LHS)>>;
|
||||
def RSBri : AsI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
|
||||
"rsb", " $dst, $a, $b",
|
||||
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
|
||||
|
||||
def RSBrs : AsI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
|
||||
"rsb", " $dst, $a, $b",
|
||||
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
|
||||
|
||||
// RSB with 's' bit set.
|
||||
let clobbersPred = 1 in {
|
||||
def RSBSri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
|
||||
"rsb", "s $dst, $a, $b",
|
||||
[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>;
|
||||
def RSBSrs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
|
||||
"rsb", "s $dst, $a, $b",
|
||||
[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>;
|
||||
}
|
||||
|
||||
// FIXME: Do not allow RSC to be predicated for now.
|
||||
def RSCri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
|
||||
"rsc $dst, $a, $b",
|
||||
// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
|
||||
def RSCri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b, cc_out:$s),
|
||||
"rsc${s} $dst, $a, $b",
|
||||
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>;
|
||||
def RSCrs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
|
||||
"rsc $dst, $a, $b",
|
||||
def RSCrs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b, cc_out:$s),
|
||||
"rsc${s} $dst, $a, $b",
|
||||
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>;
|
||||
|
||||
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
|
||||
@ -961,18 +953,18 @@ def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
|
||||
// Bitwise Instructions.
|
||||
//
|
||||
|
||||
defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
|
||||
defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
|
||||
defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
|
||||
defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
|
||||
defm AND : AsI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
|
||||
defm ORR : AsI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
|
||||
defm EOR : AsI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
|
||||
defm BIC : AsI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
|
||||
|
||||
def MVNr : AI<(ops GPR:$dst, GPR:$src),
|
||||
"mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
|
||||
def MVNs : AI<(ops GPR:$dst, so_reg:$src),
|
||||
"mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
|
||||
def MVNr : AsI<(ops GPR:$dst, GPR:$src),
|
||||
"mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
|
||||
def MVNs : AsI<(ops GPR:$dst, so_reg:$src),
|
||||
"mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
|
||||
let isReMaterializable = 1 in
|
||||
def MVNi : AI<(ops GPR:$dst, so_imm:$imm),
|
||||
"mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
|
||||
def MVNi : AsI<(ops GPR:$dst, so_imm:$imm),
|
||||
"mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
|
||||
|
||||
def : ARMPat<(and GPR:$src, so_imm_not:$imm),
|
||||
(BICri GPR:$src, so_imm_not:$imm)>;
|
||||
@ -981,46 +973,42 @@ def : ARMPat<(and GPR:$src, so_imm_not:$imm),
|
||||
// Multiply Instructions.
|
||||
//
|
||||
|
||||
// AI_orr - Defines a (op r, r) pattern.
|
||||
class AI_orr<string opc, SDNode opnode>
|
||||
: AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
||||
opc, " $dst, $a, $b",
|
||||
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
|
||||
def MUL : AsI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
||||
"mul", " $dst, $a, $b",
|
||||
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
|
||||
|
||||
// AI_oorr - Defines a (op (op r, r), r) pattern.
|
||||
class AI_oorr<string opc, SDNode opnode1, SDNode opnode2>
|
||||
: AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
|
||||
opc, " $dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (opnode1 (opnode2 GPR:$a, GPR:$b), GPR:$c))]>;
|
||||
|
||||
def MUL : AI_orr<"mul", mul>;
|
||||
def MLA : AI_oorr<"mla", add, mul>;
|
||||
def MLA : AsI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
|
||||
"mla", " $dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
|
||||
|
||||
// Extra precision multiplies with low / high results
|
||||
def SMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"smull", " $ldst, $hdst, $a, $b",
|
||||
[]>;
|
||||
def SMULL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"smull", " $ldst, $hdst, $a, $b", []>;
|
||||
|
||||
def UMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"umull", " $ldst, $hdst, $a, $b",
|
||||
[]>;
|
||||
def UMULL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"umull", " $ldst, $hdst, $a, $b", []>;
|
||||
|
||||
// Multiply + accumulate
|
||||
def SMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"smlal", " $ldst, $hdst, $a, $b",
|
||||
[]>;
|
||||
def SMLAL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"smlal", " $ldst, $hdst, $a, $b", []>;
|
||||
|
||||
def UMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"umlal", " $ldst, $hdst, $a, $b",
|
||||
[]>;
|
||||
def UMLAL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"umlal", " $ldst, $hdst, $a, $b", []>;
|
||||
|
||||
def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
||||
"umaal", " $ldst, $hdst, $a, $b",
|
||||
[]>, Requires<[IsARM, HasV6]>;
|
||||
"umaal", " $ldst, $hdst, $a, $b", []>,
|
||||
Requires<[IsARM, HasV6]>;
|
||||
|
||||
// Most significant word multiply
|
||||
def SMMUL : AI_orr<"smmul", mulhs>, Requires<[IsARM, HasV6]>;
|
||||
def SMMLA : AI_oorr<"smmla", add, mulhs>, Requires<[IsARM, HasV6]>;
|
||||
def SMMUL : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
||||
"smmul", " $dst, $a, $b",
|
||||
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
|
||||
Requires<[IsARM, HasV6]>;
|
||||
|
||||
def SMMLA : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
|
||||
"smmla", " $dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
|
||||
Requires<[IsARM, HasV6]>;
|
||||
|
||||
|
||||
def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
|
||||
@ -1164,7 +1152,6 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
|
||||
// Comparison Instructions...
|
||||
//
|
||||
|
||||
let clobbersPred = 1 in {
|
||||
defm CMP : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
|
||||
defm CMN : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
|
||||
|
||||
@ -1174,7 +1161,6 @@ defm TEQ : AI1_cmp_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0
|
||||
|
||||
defm CMPnz : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
|
||||
defm CMNnz : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
|
||||
}
|
||||
|
||||
def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
|
||||
(CMNri GPR:$src, so_imm_neg:$imm)>;
|
||||
@ -1223,8 +1209,8 @@ def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p),
|
||||
//
|
||||
|
||||
// __aeabi_read_tp preserves the registers r1-r3.
|
||||
let isCall = 1, clobbersPred = 1,
|
||||
Defs = [R0, R12, LR] in {
|
||||
let isCall = 1,
|
||||
Defs = [R0, R12, LR, CPSR] in {
|
||||
def TPsoft : AXI<(ops),
|
||||
"bl __aeabi_read_tp",
|
||||
[(set R0, ARMthread_pointer)]>;
|
||||
|
||||
@ -33,7 +33,6 @@ class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
|
||||
string asm, string cstr, list<dag> pattern>
|
||||
// FIXME: Set all opcodes to 0 for now.
|
||||
: InstARM<0, am, sz, IndexModeNone, cstr> {
|
||||
let clobbersPred = 1;
|
||||
let OperandList = ops;
|
||||
let AsmString = asm;
|
||||
let Pattern = pattern;
|
||||
|
||||
@ -275,7 +275,6 @@ def FMDRR : ADI<(ops DPR:$dst, GPR:$src1, GPR:$src2),
|
||||
|
||||
// FMSRR: GPR -> SPR
|
||||
|
||||
let clobbersPred = 1 in
|
||||
def FMSTAT : ASI<(ops), "fmstat", "", [(arm_fmstat)]>, Imp<[], [CPSR]>;
|
||||
|
||||
// FMXR: GPR -> VFP Sstem reg
|
||||
|
||||
@ -158,7 +158,7 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||
|
||||
BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase)
|
||||
.addReg(Base, false, false, BaseKill).addImm(ImmedOffset)
|
||||
.addImm(Pred).addReg(PredReg);
|
||||
.addImm(Pred).addReg(PredReg).addReg(0);
|
||||
Base = NewBase;
|
||||
BaseKill = true; // New base is always killed right its use.
|
||||
}
|
||||
|
||||
@ -191,7 +191,7 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg);
|
||||
else
|
||||
BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg)
|
||||
.addImm((int64_t)ARMCC::AL).addReg(0);
|
||||
.addImm((int64_t)ARMCC::AL).addReg(0).addReg(0);
|
||||
} else if (RC == ARM::SPRRegisterClass)
|
||||
BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg)
|
||||
.addImm((int64_t)ARMCC::AL).addReg(0);
|
||||
@ -258,6 +258,9 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
||||
switch (Opc) {
|
||||
default: break;
|
||||
case ARM::MOVr: {
|
||||
if (MI->getOperand(4).getReg() == ARM::CPSR)
|
||||
// If it is updating CPSR, then it cannot be foled.
|
||||
break;
|
||||
unsigned Pred = MI->getOperand(2).getImmedValue();
|
||||
unsigned PredReg = MI->getOperand(3).getReg();
|
||||
if (OpNum == 0) { // move -> store
|
||||
@ -454,7 +457,7 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
|
||||
// Build the new ADD / SUB.
|
||||
BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
|
||||
.addReg(BaseReg, false, false, true).addImm(SOImmVal)
|
||||
.addImm((unsigned)Pred).addReg(PredReg, false);
|
||||
.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
|
||||
BaseReg = DestReg;
|
||||
}
|
||||
}
|
||||
@ -1380,7 +1383,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
MachineInstrBuilder MIB =
|
||||
BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
|
||||
.addFrameIndex(FramePtrSpillFI).addImm(0);
|
||||
if (!isThumb) MIB.addImm(ARMCC::AL).addReg(0);
|
||||
if (!isThumb) MIB.addImm(ARMCC::AL).addReg(0).addReg(0);
|
||||
}
|
||||
|
||||
if (!isThumb) {
|
||||
@ -1496,10 +1499,11 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
|
||||
hasFP(MF))
|
||||
if (NumBytes)
|
||||
BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
|
||||
.addImm(NumBytes).addImm((unsigned)ARMCC::AL).addReg(0);
|
||||
.addImm(NumBytes)
|
||||
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
|
||||
else
|
||||
BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
|
||||
.addImm((unsigned)ARMCC::AL).addReg(0);
|
||||
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
|
||||
} else if (NumBytes) {
|
||||
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII);
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user