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[X86][BMI] Added fast-isel tests for BMI1 intrinsics
A lot of the codegen is pretty awful for these as they are mostly implemented as generic bit twiddling ops llvm-svn: 272508
This commit is contained in:
Simon Pilgrim
parent
ed661e0e70
commit
abf516f3bc
165
test/CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll
Normal file
165
test/CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll
Normal file
@ -0,0 +1,165 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/bmi-builtins.c
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;
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; AMD Intrinsics
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;
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define i64 @test__andn_u64(i64 %a0, i64 %a1) {
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; X64-LABEL: test__andn_u64:
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; X64: # BB#0:
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; X64-NEXT: xorq $-1, %rdi
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; X64-NEXT: andq %rsi, %rdi
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: retq
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%xor = xor i64 %a0, -1
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%res = and i64 %xor, %a1
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ret i64 %res
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}
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define i64 @test__bextr_u64(i64 %a0, i64 %a1) {
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; X64-LABEL: test__bextr_u64:
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; X64: # BB#0:
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; X64-NEXT: bextrq %rsi, %rdi, %rax
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; X64-NEXT: retq
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%res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %a1)
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ret i64 %res
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}
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define i64 @test__blsi_u64(i64 %a0) {
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; X64-LABEL: test__blsi_u64:
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; X64: # BB#0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: subq %rdi, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%neg = sub i64 0, %a0
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%res = and i64 %a0, %neg
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ret i64 %res
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}
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define i64 @test__blsmsk_u64(i64 %a0) {
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; X64-LABEL: test__blsmsk_u64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: xorq %rdi, %rax
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; X64-NEXT: retq
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%dec = sub i64 %a0, 1
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%res = xor i64 %a0, %dec
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ret i64 %res
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}
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define i64 @test__blsr_u64(i64 %a0) {
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; X64-LABEL: test__blsr_u64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%dec = sub i64 %a0, 1
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%res = and i64 %a0, %dec
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ret i64 %res
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}
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define i64 @test__tzcnt_u64(i64 %a0) {
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; X64-LABEL: test__tzcnt_u64:
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; X64: # BB#0:
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; X64-NEXT: movl $64, %ecx
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; X64-NEXT: tzcntq %rdi, %rax
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; X64-NEXT: cmovbq %rcx, %rax
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; X64-NEXT: retq
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%cmp = icmp ne i64 %a0, 0
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%cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 true)
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%res = select i1 %cmp, i64 %cttz, i64 64
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ret i64 %res
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}
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;
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; Intel intrinsics
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;
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define i64 @test_andn_u64(i64 %a0, i64 %a1) {
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; X64-LABEL: test_andn_u64:
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; X64: # BB#0:
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; X64-NEXT: xorq $-1, %rdi
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; X64-NEXT: andq %rsi, %rdi
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: retq
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%xor = xor i64 %a0, -1
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%res = and i64 %xor, %a1
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ret i64 %res
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}
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define i64 @test_bextr_u64(i64 %a0, i32 %a1, i32 %a2) {
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; X64-LABEL: test_bextr_u64:
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; X64: # BB#0:
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; X64-NEXT: andl $255, %esi
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; X64-NEXT: andl $255, %edx
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; X64-NEXT: shll $8, %edx
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; X64-NEXT: orl %esi, %edx
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; X64-NEXT: movl %edx, %eax
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; X64-NEXT: bextrq %rax, %rdi, %rax
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; X64-NEXT: retq
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%and1 = and i32 %a1, 255
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%and2 = and i32 %a2, 255
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%shl = shl i32 %and2, 8
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%or = or i32 %and1, %shl
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%zext = zext i32 %or to i64
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%res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %zext)
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ret i64 %res
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}
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define i64 @test_blsi_u64(i64 %a0) {
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; X64-LABEL: test_blsi_u64:
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; X64: # BB#0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: subq %rdi, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%neg = sub i64 0, %a0
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%res = and i64 %a0, %neg
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ret i64 %res
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}
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define i64 @test_blsmsk_u64(i64 %a0) {
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; X64-LABEL: test_blsmsk_u64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: xorq %rdi, %rax
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; X64-NEXT: retq
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%dec = sub i64 %a0, 1
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%res = xor i64 %a0, %dec
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ret i64 %res
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}
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define i64 @test_blsr_u64(i64 %a0) {
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; X64-LABEL: test_blsr_u64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%dec = sub i64 %a0, 1
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%res = and i64 %a0, %dec
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ret i64 %res
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}
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define i64 @test_tzcnt_u64(i64 %a0) {
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; X64-LABEL: test_tzcnt_u64:
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; X64: # BB#0:
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; X64-NEXT: movl $64, %ecx
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; X64-NEXT: tzcntq %rdi, %rax
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; X64-NEXT: cmovbq %rcx, %rax
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; X64-NEXT: retq
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%cmp = icmp ne i64 %a0, 0
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%cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 true)
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%res = select i1 %cmp, i64 %cttz, i64 64
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ret i64 %res
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}
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declare i64 @llvm.cttz.i64(i64, i1)
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declare i64 @llvm.x86.bmi.bextr.64(i64, i64)
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326
test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
Normal file
326
test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
Normal file
@ -0,0 +1,326 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/bmi-builtins.c
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;
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; AMD Intrinsics
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;
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define i16 @test__tzcnt_u16(i16 %a0) {
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; X32-LABEL: test__tzcnt_u16:
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; X32: # BB#0:
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; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movzwl %ax, %ecx
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; X32-NEXT: cmpl $0, %ecx
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; X32-NEXT: jne .LBB0_1
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; X32-NEXT: # BB#2:
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; X32-NEXT: movw $16, %ax
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; X32-NEXT: retl
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; X32-NEXT: .LBB0_1:
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; X32-NEXT: tzcntw %ax, %ax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__tzcnt_u16:
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; X64: # BB#0:
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; X64-NEXT: movw $16, %cx
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; X64-NEXT: movzwl %di, %edx
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; X64-NEXT: tzcntw %dx, %ax
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; X64-NEXT: cmpl $0, %edx
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; X64-NEXT: cmovew %cx, %ax
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; X64-NEXT: retq
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%zext = zext i16 %a0 to i32
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%cmp = icmp ne i32 %zext, 0
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%cttz = call i16 @llvm.cttz.i16(i16 %a0, i1 true)
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%res = select i1 %cmp, i16 %cttz, i16 16
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ret i16 %res
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}
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define i32 @test__andn_u32(i32 %a0, i32 %a1) {
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; X32-LABEL: test__andn_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: xorl $-1, %eax
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; X32-NEXT: andl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__andn_u32:
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; X64: # BB#0:
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; X64-NEXT: xorl $-1, %edi
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; X64-NEXT: andl %esi, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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%xor = xor i32 %a0, -1
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%res = and i32 %xor, %a1
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ret i32 %res
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}
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define i32 @test__bextr_u32(i32 %a0, i32 %a1) {
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; X32-LABEL: test__bextr_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__bextr_u32:
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; X64: # BB#0:
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; X64-NEXT: bextrl %esi, %edi, %eax
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; X64-NEXT: retq
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%res = call i32 @llvm.x86.bmi.bextr.32(i32 %a0, i32 %a1)
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ret i32 %res
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}
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define i32 @test__blsi_u32(i32 %a0) {
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; X32-LABEL: test__blsi_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: subl %ecx, %eax
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; X32-NEXT: andl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blsi_u32:
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; X64: # BB#0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: subl %edi, %eax
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; X64-NEXT: andl %edi, %eax
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; X64-NEXT: retq
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%neg = sub i32 0, %a0
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%res = and i32 %a0, %neg
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ret i32 %res
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}
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define i32 @test__blsmsk_u32(i32 %a0) {
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; X32-LABEL: test__blsmsk_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl %ecx, %eax
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; X32-NEXT: subl $1, %eax
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; X32-NEXT: xorl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blsmsk_u32:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: subl $1, %eax
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; X64-NEXT: xorl %edi, %eax
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; X64-NEXT: retq
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%dec = sub i32 %a0, 1
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%res = xor i32 %a0, %dec
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ret i32 %res
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}
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define i32 @test__blsr_u32(i32 %a0) {
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; X32-LABEL: test__blsr_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl %ecx, %eax
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; X32-NEXT: subl $1, %eax
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; X32-NEXT: andl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blsr_u32:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: subl $1, %eax
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; X64-NEXT: andl %edi, %eax
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; X64-NEXT: retq
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%dec = sub i32 %a0, 1
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%res = and i32 %a0, %dec
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ret i32 %res
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}
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define i32 @test__tzcnt_u32(i32 %a0) {
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; X32-LABEL: test__tzcnt_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: cmpl $0, %eax
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; X32-NEXT: jne .LBB6_1
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; X32-NEXT: # BB#2:
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; X32-NEXT: movl $32, %eax
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; X32-NEXT: retl
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; X32-NEXT: .LBB6_1:
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; X32-NEXT: tzcntl %eax, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__tzcnt_u32:
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; X64: # BB#0:
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; X64-NEXT: movl $32, %ecx
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; X64-NEXT: tzcntl %edi, %eax
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; X64-NEXT: cmovbl %ecx, %eax
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; X64-NEXT: retq
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%cmp = icmp ne i32 %a0, 0
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%cttz = call i32 @llvm.cttz.i32(i32 %a0, i1 true)
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%res = select i1 %cmp, i32 %cttz, i32 32
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ret i32 %res
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}
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;
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; Intel intrinsics
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;
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define i16 @test_tzcnt_u16(i16 %a0) {
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; X32-LABEL: test_tzcnt_u16:
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; X32: # BB#0:
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; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movzwl %ax, %ecx
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; X32-NEXT: cmpl $0, %ecx
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; X32-NEXT: jne .LBB7_1
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; X32-NEXT: # BB#2:
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; X32-NEXT: movw $16, %ax
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; X32-NEXT: retl
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; X32-NEXT: .LBB7_1:
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; X32-NEXT: tzcntw %ax, %ax
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; X32-NEXT: retl
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;
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; X64-LABEL: test_tzcnt_u16:
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; X64: # BB#0:
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; X64-NEXT: movw $16, %cx
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; X64-NEXT: movzwl %di, %edx
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; X64-NEXT: tzcntw %dx, %ax
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; X64-NEXT: cmpl $0, %edx
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; X64-NEXT: cmovew %cx, %ax
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; X64-NEXT: retq
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%zext = zext i16 %a0 to i32
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%cmp = icmp ne i32 %zext, 0
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%cttz = call i16 @llvm.cttz.i16(i16 %a0, i1 true)
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%res = select i1 %cmp, i16 %cttz, i16 16
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ret i16 %res
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}
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define i32 @test_andn_u32(i32 %a0, i32 %a1) {
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; X32-LABEL: test_andn_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: xorl $-1, %eax
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; X32-NEXT: andl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test_andn_u32:
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; X64: # BB#0:
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; X64-NEXT: xorl $-1, %edi
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; X64-NEXT: andl %esi, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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%xor = xor i32 %a0, -1
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%res = and i32 %xor, %a1
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ret i32 %res
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}
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define i32 @test_bextr_u32(i32 %a0, i32 %a1, i32 %a2) {
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; X32-LABEL: test_bextr_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: andl $255, %ecx
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; X32-NEXT: andl $255, %eax
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; X32-NEXT: shll $8, %eax
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; X32-NEXT: orl %ecx, %eax
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; X32-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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;
|
||||
; X64-LABEL: test_bextr_u32:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: andl $255, %esi
|
||||
; X64-NEXT: andl $255, %edx
|
||||
; X64-NEXT: shll $8, %edx
|
||||
; X64-NEXT: orl %esi, %edx
|
||||
; X64-NEXT: bextrl %edx, %edi, %eax
|
||||
; X64-NEXT: retq
|
||||
%and1 = and i32 %a1, 255
|
||||
%and2 = and i32 %a2, 255
|
||||
%shl = shl i32 %and2, 8
|
||||
%or = or i32 %and1, %shl
|
||||
%res = call i32 @llvm.x86.bmi.bextr.32(i32 %a0, i32 %or)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_blsi_u32(i32 %a0) {
|
||||
; X32-LABEL: test_blsi_u32:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: subl %ecx, %eax
|
||||
; X32-NEXT: andl %ecx, %eax
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_blsi_u32:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: subl %edi, %eax
|
||||
; X64-NEXT: andl %edi, %eax
|
||||
; X64-NEXT: retq
|
||||
%neg = sub i32 0, %a0
|
||||
%res = and i32 %a0, %neg
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_blsmsk_u32(i32 %a0) {
|
||||
; X32-LABEL: test_blsmsk_u32:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: movl %ecx, %eax
|
||||
; X32-NEXT: subl $1, %eax
|
||||
; X32-NEXT: xorl %ecx, %eax
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_blsmsk_u32:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: subl $1, %eax
|
||||
; X64-NEXT: xorl %edi, %eax
|
||||
; X64-NEXT: retq
|
||||
%dec = sub i32 %a0, 1
|
||||
%res = xor i32 %a0, %dec
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_blsr_u32(i32 %a0) {
|
||||
; X32-LABEL: test_blsr_u32:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: movl %ecx, %eax
|
||||
; X32-NEXT: subl $1, %eax
|
||||
; X32-NEXT: andl %ecx, %eax
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_blsr_u32:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: subl $1, %eax
|
||||
; X64-NEXT: andl %edi, %eax
|
||||
; X64-NEXT: retq
|
||||
%dec = sub i32 %a0, 1
|
||||
%res = and i32 %a0, %dec
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @test_tzcnt_u32(i32 %a0) {
|
||||
; X32-LABEL: test_tzcnt_u32:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-NEXT: cmpl $0, %eax
|
||||
; X32-NEXT: jne .LBB13_1
|
||||
; X32-NEXT: # BB#2:
|
||||
; X32-NEXT: movl $32, %eax
|
||||
; X32-NEXT: retl
|
||||
; X32-NEXT: .LBB13_1:
|
||||
; X32-NEXT: tzcntl %eax, %eax
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_tzcnt_u32:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: movl $32, %ecx
|
||||
; X64-NEXT: tzcntl %edi, %eax
|
||||
; X64-NEXT: cmovbl %ecx, %eax
|
||||
; X64-NEXT: retq
|
||||
%cmp = icmp ne i32 %a0, 0
|
||||
%cttz = call i32 @llvm.cttz.i32(i32 %a0, i1 true)
|
||||
%res = select i1 %cmp, i32 %cttz, i32 32
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
declare i16 @llvm.cttz.i16(i16, i1)
|
||||
declare i32 @llvm.cttz.i32(i32, i1)
|
||||
declare i32 @llvm.x86.bmi.bextr.32(i32, i32)
|
||||
Loading…
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Reference in New Issue
Block a user