RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-02 10:21:54 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix a miscompile in 186.crafty for Thumb2 that was exposed by Evan's

Browse Source 
scheduling change in svn 115121.  The CriticalAntiDepBreaker had bad
liveness information.  It was calculating the KillIndices for one scheduling
region in a basic block, rescheduling that region so the KillIndices were
no longer valid, and then using those wrong KillIndices to make decisions
for the next scheduling region.  I've not been able to reduce a small
testcase for this.  Radar 8502534.

llvm-svn: 115400
This commit is contained in:
Bob Wilson 2010-10-02 01:49:29 +00:00
parent 2fd7de3006
commit ac095e1026
1 changed files with 14 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -130,21 +130,25 @@ void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
return;
assert(Count < InsertPosIndex && "Instruction index out of expected range!");
// Any register which was defined within the previous scheduling region
// may have been rescheduled and its lifetime may overlap with registers
// in ways not reflected in our current liveness state. For each such
// register, adjust the liveness state to be conservatively correct.
for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
// Mark this register to be non-renamable.
for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
if (KillIndices[Reg] != ~0u) {
// If Reg is currently live, then mark that it can't be renamed as
// we don't know the extent of its live-range anymore (now that it
// has been scheduled).
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = Count;
} else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
// Any register which was defined within the previous scheduling region
// may have been rescheduled and its lifetime may overlap with registers
// in ways not reflected in our current liveness state. For each such
// register, adjust the liveness state to be conservatively correct.
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
// Move the def index to the end of the previous region, to reflect
// that the def could theoretically have been scheduled at the end.
DefIndices[Reg] = InsertPosIndex;
}
}
PrescanInstruction(MI);
ScanInstruction(MI, Count);
@ -580,7 +584,7 @@ BreakAntiDependencies(const std::vector<SUnit>& SUnits,
}
// We just went back in time and modified history; the
// liveness information for the anti-depenence reg is now
// liveness information for the anti-dependence reg is now
// inconsistent. Set the state as if it were dead.
Classes[NewReg] = Classes[AntiDepReg];
DefIndices[NewReg] = DefIndices[AntiDepReg];