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32-to-64-bit sext_inreg pattern.

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llvm-svn: 147004
This commit is contained in:
Akira Hatanaka 2011-12-20 22:40:40 +00:00
parent 13f23f5895
commit ad193d95ae
2 changed files with 13 additions and 0 deletions
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5
lib/Target/Mips/Mips64InstrInfo.td
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@ -215,6 +215,8 @@ def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
"sll\t$rd, $rt, 0", [], IIAlu>;
def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
"sll\t$rd, $rt, 0", [], IIAlu>;
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
@ -311,3 +313,6 @@ def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
// Sign extend in register
def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>;

8
test/CodeGen/Mips/mips64ext.ll
View File

@ -9,3 +9,11 @@ entry:
%conv = zext i32 %add to i64
ret i64 %conv
}
define i64 @sext64_32(i32 %a) nounwind readnone {
entry:
; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0
%conv = sext i32 %a to i64
ret i64 %conv
}