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R600: Expand vector FRINT ops
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
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@ -154,6 +154,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FDIV, VT, Expand);
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setOperationAction(ISD::FFLOOR, VT, Expand);
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setOperationAction(ISD::FMUL, VT, Expand);
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setOperationAction(ISD::FRINT, VT, Expand);
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setOperationAction(ISD::FSUB, VT, Expand);
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}
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}
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54
test/CodeGen/R600/llvm.rint.ll
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54
test/CodeGen/R600/llvm.rint.ll
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@ -0,0 +1,54 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @f32
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; R600-CHECK: RNDNE
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; SI-CHECK: @f32
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; SI-CHECK: V_RNDNE_F32_e32
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define void @f32(float addrspace(1)* %out, float %in) {
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entry:
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%0 = call float @llvm.rint.f32(float %in)
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store float %0, float addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @v2f32
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; R600-CHECK: RNDNE
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; R600-CHECK: RNDNE
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; SI-CHECK: @v2f32
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; SI-CHECK: V_RNDNE_F32_e32
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; SI-CHECK: V_RNDNE_F32_e32
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define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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entry:
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%0 = call <2 x float> @llvm.rint.v2f32(<2 x float> %in)
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @v4f32
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; R600-CHECK: RNDNE
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; R600-CHECK: RNDNE
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; R600-CHECK: RNDNE
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; R600-CHECK: RNDNE
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; SI-CHECK: @v4f32
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; SI-CHECK: V_RNDNE_F32_e32
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; SI-CHECK: V_RNDNE_F32_e32
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; SI-CHECK: V_RNDNE_F32_e32
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; SI-CHECK: V_RNDNE_F32_e32
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define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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entry:
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%0 = call <4 x float> @llvm.rint.v4f32(<4 x float> %in)
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store <4 x float> %0, <4 x float> addrspace(1)* %out
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ret void
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}
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; Function Attrs: nounwind readonly
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declare float @llvm.rint.f32(float) #0
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; Function Attrs: nounwind readonly
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declare <2 x float> @llvm.rint.v2f32(<2 x float>) #0
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; Function Attrs: nounwind readonly
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declare <4 x float> @llvm.rint.v4f32(<4 x float>) #0
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attributes #0 = { nounwind readonly }
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