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Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
This commit is contained in:
Jim Grosbach
parent
5bf752bcf4
commit
aebb9cdf68
@ -1975,10 +1975,12 @@ def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
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multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
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InstrItinClass itin, InstrItinClass itin_upd> {
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// IA is the default, so no need for an explicit suffix on the
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// mnemonic here. Without it is the cannonical spelling.
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def IA :
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AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, f, itin,
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!strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
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!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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@ -1986,7 +1988,7 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
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def IA_UPD :
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AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, f, itin_upd,
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!strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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@ -2052,10 +2054,11 @@ defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
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} // neverHasSideEffects
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// Load / Store Multiple Mnemonic Aliases
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def : MnemonicAlias<"ldmfd", "ldmia">;
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def : MnemonicAlias<"ldmfd", "ldm">;
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def : MnemonicAlias<"ldmia", "ldm">;
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def : MnemonicAlias<"stmfd", "stmdb">;
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def : MnemonicAlias<"ldm", "ldmia">;
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def : MnemonicAlias<"stm", "stmia">;
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def : MnemonicAlias<"stmia", "stm">;
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def : MnemonicAlias<"stmea", "stm">;
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// FIXME: remove when we have a way to marking a MI with these properties.
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// FIXME: Should pc be an implicit operand like PICADD, etc?
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@ -20,50 +20,6 @@
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@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
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vqdmull.s32 q8, d17, d16
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@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9]
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@ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8]
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@ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9]
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@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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ldm r2, {r1,r3-r6,sp}
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ldmia r2, {r1,r3-r6,sp}
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ldmib r2, {r1,r3-r6,sp}
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ldmda r2, {r1,r3-r6,sp}
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ldmdb r2, {r1,r3-r6,sp}
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ldmfd r2, {r1,r3-r6,sp}
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@ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
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@ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
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@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9]
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@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8]
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@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9]
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@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9]
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stm r2, {r1,r3-r6,sp}
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stmia r2, {r1,r3-r6,sp}
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stmib r2, {r1,r3-r6,sp}
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stmda r2, {r1,r3-r6,sp}
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stmdb r2, {r1,r3-r6,sp}
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stmfd r2, {r1,r3-r6,sp}
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@ CHECK: ldmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8]
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@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
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@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
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@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
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ldmia r2!, {r1,r3-r6,sp}
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ldmib r2!, {r1,r3-r6,sp}
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ldmda r2!, {r1,r3-r6,sp}
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ldmdb r2!, {r1,r3-r6,sp}
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@ CHECK: stmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8]
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@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9]
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@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8]
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@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9]
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stmia r2!, {r1,r3-r6,sp}
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stmib r2!, {r1,r3-r6,sp}
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stmda r2!, {r1,r3-r6,sp}
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stmdb r2!, {r1,r3-r6,sp}
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@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
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and r1,r2,r3
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@ -588,3 +588,61 @@ _func:
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@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
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@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
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@------------------------------------------------------------------------------
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@ LDM*
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@------------------------------------------------------------------------------
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ldm r2, {r1,r3-r6,sp}
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ldmia r2, {r1,r3-r6,sp}
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ldmib r2, {r1,r3-r6,sp}
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ldmda r2, {r1,r3-r6,sp}
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ldmdb r2, {r1,r3-r6,sp}
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ldmfd r2, {r1,r3-r6,sp}
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@ with update
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ldm r2!, {r1,r3-r6,sp}
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ldmib r2!, {r1,r3-r6,sp}
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ldmda r2!, {r1,r3-r6,sp}
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ldmdb r2!, {r1,r3-r6,sp}
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@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9]
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@ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8]
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@ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9]
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@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldm r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8]
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@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
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@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
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@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
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@------------------------------------------------------------------------------
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@ STM*
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@------------------------------------------------------------------------------
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stm r2, {r1,r3-r6,sp}
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stmia r2, {r1,r3-r6,sp}
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stmib r2, {r1,r3-r6,sp}
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stmda r2, {r1,r3-r6,sp}
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stmdb r2, {r1,r3-r6,sp}
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stmfd r2, {r1,r3-r6,sp}
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@ with update
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stmia r2!, {r1,r3-r6,sp}
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stmib r2!, {r1,r3-r6,sp}
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stmda r2!, {r1,r3-r6,sp}
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stmdb r2!, {r1,r3-r6,sp}
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@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
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@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
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@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9]
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@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8]
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@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9]
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@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9]
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@ CHECK: stm r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8]
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@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9]
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@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8]
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@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9]
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