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add copy of comment to the code that will survive the mcjit'ization
llvm-svn: 119308
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@ -199,6 +199,8 @@ unsigned PPCMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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// MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
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// The GPR operand should come through here though.
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assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
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MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
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return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
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