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MC] Provide an MCTargetOptions to implementors of MCAsmBackendCtorTy, NFC

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Some targets, notably AArch64 for ILP32, have different relocation encodings
based upon the ABI. This is an enabling change, so a future patch can use the
ABIName from MCTargetOptions to chose which relocations to use. Tested using
check-llvm.

The corresponding change to clang is in: http://reviews.llvm.org/D16538

Patch by: Joel Jones

Differential Revision: https://reviews.llvm.org/D16213

llvm-svn: 276654
This commit is contained in:
Joel Jones 2016-07-25 17:18:28 +00:00
parent 199957b97b
commit b127877693
25 changed files with 114 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
include/llvm/Support/TargetRegistry.h
View File

@ -112,7 +112,8 @@ public:
TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
const MCTargetOptions &Options);
@ -365,10 +366,12 @@ public:
///
/// \param TheTriple The target triple string.
MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
StringRef TheTriple, StringRef CPU) const {
StringRef TheTriple, StringRef CPU,
const MCTargetOptions &Options)
const {
if (!MCAsmBackendCtorFn)
return nullptr;
return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU);
return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU, Options);
}
/// createMCAsmParser - Create a target specific assembly parser.
@ -1071,7 +1074,8 @@ template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
private:
static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
const Triple &TheTriple, StringRef CPU) {
const Triple &TheTriple, StringRef CPU,
const MCTargetOptions &Options) {
return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
}
};

9
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -224,7 +224,8 @@ bool LLVMTargetMachine::addPassesToEmitFile(
MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
MCAsmBackend *MAB =
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
Options.MCOptions);
auto FOut = llvm::make_unique<formatted_raw_ostream>(Out);
MCStreamer *S = getTarget().createAsmStreamer(
*Context, std::move(FOut), Options.MCOptions.AsmVerbose,
@ -238,7 +239,8 @@ bool LLVMTargetMachine::addPassesToEmitFile(
// emission fails.
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
MCAsmBackend *MAB =
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
Options.MCOptions);
if (!MCE || !MAB)
return true;
@ -293,7 +295,8 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
MCCodeEmitter *MCE =
getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
MCAsmBackend *MAB =
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
Options.MCOptions);
if (!MCE || !MAB)
return true;

9
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
View File

@ -574,7 +574,8 @@ void ELFAArch64AsmBackend::processFixupValue(
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TheTriple,
StringRef CPU) {
StringRef CPU,
const MCTargetOptions &Options) {
if (TheTriple.isOSBinFormatMachO())
return new DarwinAArch64AsmBackend(T, MRI);
@ -586,10 +587,10 @@ MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TheTriple,
StringRef CPU) {
StringRef CPU,
const MCTargetOptions &Options) {
assert(TheTriple.isOSBinFormatELF() &&
"Big endian is only supported for ELF targets!");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
return new ELFAArch64AsmBackend(T, OSABI,
/*IsLittleEndian=*/false);
return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/false);
}

7
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
View File

@ -27,6 +27,7 @@ class MCRegisterInfo;
class MCObjectWriter;
class MCStreamer;
class MCSubtargetInfo;
class MCTargetOptions;
class MCTargetStreamer;
class StringRef;
class Target;
@ -43,10 +44,12 @@ MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx);
MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createAArch64beAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI,

3
lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
View File

@ -171,7 +171,8 @@ public:
MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
// Use 64-bit ELF for amdgcn
return new ELFAMDGPUAsmBackend(T, TT);
}

4
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
View File

@ -27,6 +27,7 @@ class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class Target;
class Triple;
class raw_pwrite_stream;
@ -44,7 +45,8 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
bool HasRelocationAddend,

21
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@ -1111,6 +1111,7 @@ static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TheTriple, StringRef CPU,
const MCTargetOptions &Options,
bool isLittle) {
switch (TheTriple.getObjectFormat()) {
default:
@ -1131,24 +1132,28 @@ MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, true);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
}
MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, false);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
}
MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, true);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
}
MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, false);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
}

14
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@ -28,6 +28,7 @@ class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCStreamer;
class MCTargetOptions;
class MCRelocationInfo;
class MCTargetStreamer;
class StringRef;
@ -66,21 +67,26 @@ MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options,
bool IsLittleEndian);
MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createThumbLEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createThumbBEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
// Construct a PE/COFF machine code streamer which will generate a PE/COFF
// object file.

6
lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
View File

@ -96,12 +96,14 @@ MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions&) {
return new BPFAsmBackend(/*IsLittleEndian=*/true);
}
MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions&) {
return new BPFAsmBackend(/*IsLittleEndian=*/false);
}

7
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
View File

@ -25,6 +25,7 @@ class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class StringRef;
class Target;
class Triple;
@ -43,9 +44,11 @@ MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx);
MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, bool IsLittleEndian);

3
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
View File

@ -745,7 +745,8 @@ public:
namespace llvm {
MCAsmBackend *createHexagonAsmBackend(Target const &T,
MCRegisterInfo const & /*MRI*/,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new HexagonAsmBackend(T, OSABI, CPU);
}

4
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
View File

@ -28,6 +28,7 @@ class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class Target;
class Triple;
class StringRef;
@ -47,7 +48,8 @@ MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
MCAsmBackend *createHexagonAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, StringRef CPU);

12
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
View File

@ -482,27 +482,31 @@ void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
// MCAsmBackend
MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
/*Is64Bit*/ false);
}
MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
/*Is64Bit*/ false);
}
MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
}
MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
/*Is64Bit*/ true);
}

13
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
View File

@ -24,6 +24,7 @@ class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class StringRef;
class Target;
class Triple;
@ -44,16 +45,20 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
bool IsLittleEndian, bool Is64Bit);

3
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
View File

@ -230,7 +230,8 @@ namespace {
MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
if (TT.isOSDarwin())
return new DarwinPPCAsmBackend(T);

4
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
View File

@ -28,6 +28,7 @@ class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class Target;
class Triple;
class StringRef;
@ -43,7 +44,8 @@ MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx);
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
/// Construct an PPC ELF object writer.
MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,

3
lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
View File

@ -300,6 +300,7 @@ namespace {
MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
return new ELFSparcAsmBackend(T, TT.getOS());
}

4
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
View File

@ -24,6 +24,7 @@ class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class Target;
class Triple;
class StringRef;
@ -38,7 +39,8 @@ MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
bool IsLIttleEndian, uint8_t OSABI);
} // End llvm namespace

3
lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
View File

@ -112,7 +112,8 @@ bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new SystemZMCAsmBackend(OSABI);
}

4
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
View File

@ -21,6 +21,7 @@ class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class StringRef;
class Target;
class Triple;
@ -85,7 +86,8 @@ MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
} // end namespace llvm

6
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
View File

@ -837,7 +837,8 @@ public:
MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TheTriple,
StringRef CPU) {
StringRef CPU,
const MCTargetOptions &Options) {
if (TheTriple.isOSBinFormatMachO())
return new DarwinX86_32AsmBackend(T, MRI, CPU);
@ -855,7 +856,8 @@ MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TheTriple,
StringRef CPU) {
StringRef CPU,
const MCTargetOptions &Options) {
if (TheTriple.isOSBinFormatMachO()) {
MachO::CPUSubTypeX86 CS =
StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())

7
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
View File

@ -27,6 +27,7 @@ class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCRelocationInfo;
class MCTargetOptions;
class Target;
class Triple;
class StringRef;
@ -69,9 +70,11 @@ MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx);
MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
/// Construct an X86 Windows COFF machine code streamer which will generate
/// PE/COFF format object files.

3
tools/dsymutil/DwarfLinker.cpp
View File

@ -597,7 +597,8 @@ bool DwarfStreamer::init(Triple TheTriple, StringRef OutputFilename) {
MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, CodeModel::Default, *MC);
MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "");
MCTargetOptions Options;
MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options);
if (!MAB)
return error("no asm backend for target " + TripleName, Context);

3
tools/llvm-dwp/llvm-dwp.cpp
View File

@ -643,7 +643,8 @@ int main(int argc, char **argv) {
MCContext MC(MAI.get(), MRI.get(), &MOFI);
MOFI.InitMCObjectFileInfo(TheTriple, /*PIC*/ false, CodeModel::Default, MC);
auto MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "");
MCTargetOptions Options;
auto MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options);
if (!MAB)
return error("no asm backend for target " + TripleName, Context);

5
tools/llvm-mc/llvm-mc.cpp
View File

@ -503,7 +503,7 @@ int main(int argc, char **argv) {
MCAsmBackend *MAB = nullptr;
if (ShowEncoding) {
CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions);
}
auto FOut = llvm::make_unique<formatted_raw_ostream>(*OS);
Str.reset(TheTarget->createAsmStreamer(
@ -524,7 +524,8 @@ int main(int argc, char **argv) {
}
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU,
MCOptions);
Str.reset(TheTarget->createMCObjectStreamer(
TheTriple, Ctx, *MAB, *OS, CE, *STI, MCOptions.MCRelaxAll,
MCOptions.MCIncrementalLinkerCompatible,