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Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.

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Patch by Chris Lidbury.

llvm-svn: 163321
This commit is contained in:
Tim Northover 2012-09-06 15:17:49 +00:00
parent e02da03f09
commit b12fa01bc6
6 changed files with 131 additions and 8 deletions
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46
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -3710,8 +3710,16 @@ static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
if (fieldFromInstruction(Insn, 6, 1))
return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 4, 2) != 0)
align = 4;
switch (fieldFromInstruction(Insn, 4, 2)) {
case 0 :
align = 0; break;
case 3:
align = 4; break;
default:
return MCDisassembler::Fail;
}
break;
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@ -3769,8 +3777,16 @@ static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
if (fieldFromInstruction(Insn, 6, 1))
return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 4, 2) != 0)
align = 4;
switch (fieldFromInstruction(Insn, 4, 2)) {
case 0:
align = 0; break;
case 3:
align = 4; break;
default:
return MCDisassembler::Fail;
}
break;
}
if (Rm != 0xF) { // Writeback
@ -4090,8 +4106,15 @@ static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
inc = 2;
break;
case 2:
if (fieldFromInstruction(Insn, 4, 2))
align = 4 << fieldFromInstruction(Insn, 4, 2);
switch (fieldFromInstruction(Insn, 4, 2)) {
case 0:
align = 0; break;
case 3:
return MCDisassembler::Fail;
default:
align = 4 << fieldFromInstruction(Insn, 4, 2); break;
}
index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 6, 1))
inc = 2;
@ -4164,8 +4187,15 @@ static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
inc = 2;
break;
case 2:
if (fieldFromInstruction(Insn, 4, 2))
align = 4 << fieldFromInstruction(Insn, 4, 2);
switch (fieldFromInstruction(Insn, 4, 2)) {
case 0:
align = 0; break;
case 3:
return MCDisassembler::Fail;
default:
align = 4 << fieldFromInstruction(Insn, 4, 2); break;
}
index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 6, 1))
inc = 2;

4
test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt Normal file
View File

@ -0,0 +1,4 @@
# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
0xa0 0xf9 0x10 0x08
# CHECK: invalid instruction encoding

4
test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt Normal file
View File

@ -0,0 +1,4 @@
# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
0xa0 0xf9 0x30 0x0b
# CHECK: invalid instruction encoding

4
test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt Normal file
View File

@ -0,0 +1,4 @@
# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
0x80 0xf9 0x10 0x08
# CHECK: invalid instruction encoding

4
test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt Normal file
View File

@ -0,0 +1,4 @@
# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
0x80 0xf9 0x30 0x0b
# CHECK: invalid instruction encoding

77
test/MC/Disassembler/ARM/neont-VLD-reencoding.txt Normal file
View File

@ -0,0 +1,77 @@
# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s | FileCheck %s
0xa0 0xf9 0x00 0x00
0xa0 0xf9 0x20 0x00
0xa0 0xf9 0x40 0x00
0xa0 0xf9 0x60 0x00
0xa0 0xf9 0x80 0x00
0xa0 0xf9 0xa0 0x00
0xa0 0xf9 0xc0 0x00
0xa0 0xf9 0xe0 0x00
# CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
# CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
# CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
# CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
# CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
# CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
# CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
# CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
0xa0 0xf9 0x00 0x04
0xa0 0xf9 0x10 0x04
0xa0 0xf9 0x40 0x04
0xa0 0xf9 0x50 0x04
0xa0 0xf9 0x80 0x04
0xa0 0xf9 0x90 0x04
0xa0 0xf9 0xc0 0x04
0xa0 0xf9 0xd0 0x04
# CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
# CHECK: vld1.16 {d0[0]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
# CHECK: vld1.16 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x04]
# CHECK: vld1.16 {d0[1]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x50,0x04]
# CHECK: vld1.16 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x04]
# CHECK: vld1.16 {d0[2]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x90,0x04]
# CHECK: vld1.16 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x04]
# CHECK: vld1.16 {d0[3]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04]
0xa0 0xf9 0x00 0x08
0xa0 0xf9 0x30 0x08
0xa0 0xf9 0x80 0x08
0xa0 0xf9 0xb0 0x08
# CHECK: vld1.32 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x08]
# CHECK: vld1.32 {d0[0]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0x30,0x08]
# CHECK: vld1.32 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x08]
# CHECK: vld1.32 {d0[1]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08]
0xa0 0xf9 0x1f 0x04
0xa0 0xf9 0x8f 0x00
# CHECK: vld1.16 {d0[0]}, [r0, :16] @ encoding: [0xa0,0xf9,0x1f,0x04]
# CHECK: vld1.8 {d0[4]}, [r0] @ encoding: [0xa0,0xf9,0x8f,0x00]
0xa0 0xf9 0x1d 0x04
0xa0 0xf9 0x8d 0x00
# CHECK: vld1.16 {d0[0]}, [r0, :16]! @ encoding: [0xa0,0xf9,0x1d,0x04]
# CHECK: vld1.8 {d0[4]}, [r0]! @ encoding: [0xa0,0xf9,0x8d,0x00]
0xa5 0xf9 0x10 0x04
0xa5 0xf9 0x1a 0x04
0xae 0xf9 0x1a 0x04
0xa5 0xf9 0x1a 0x94
# CHECK: vld1.16 {d0[0]}, [r5, :16], r0 @ encoding: [0xa5,0xf9,0x10,0x04]
# CHECK: vld1.16 {d0[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04]
# CHECK: vld1.16 {d0[0]}, [lr, :16], r10 @ encoding: [0xae,0xf9,0x1a,0x04]
# CHECK: vld1.16 {d9[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94]
0xa0 0xf9 0x20 0x0b
0xa0 0xf9 0x20 0x07
0xa0 0xf9 0x20 0x03
# CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0, :128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b]
# CHECK: vld4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x07]
# CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x03]