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Add AVX2 VPMOVMASK instructions and intrinsics.
llvm-svn: 143904
This commit is contained in:
Craig Topper
parent
d422190c0f
commit
b1ef950217
@ -1744,6 +1744,33 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
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llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
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}
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// Conditional load ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx2_maskload_d : GCCBuiltin<"__builtin_ia32_maskloadd">,
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Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_v4i32_ty], [IntrReadMem]>;
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def int_x86_avx2_maskload_q : GCCBuiltin<"__builtin_ia32_maskloadq">,
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Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_v2i64_ty], [IntrReadMem]>;
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def int_x86_avx2_maskload_d_256 : GCCBuiltin<"__builtin_ia32_maskloadd256">,
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Intrinsic<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_v8i32_ty], [IntrReadMem]>;
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def int_x86_avx2_maskload_q_256 : GCCBuiltin<"__builtin_ia32_maskloadq256">,
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Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_v4i64_ty], [IntrReadMem]>;
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}
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// Conditional store ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx2_maskstore_d : GCCBuiltin<"__builtin_ia32_maskstored">,
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Intrinsic<[], [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty], []>;
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def int_x86_avx2_maskstore_q : GCCBuiltin<"__builtin_ia32_maskstoreq">,
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Intrinsic<[], [llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty], []>;
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def int_x86_avx2_maskstore_d_256 :
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GCCBuiltin<"__builtin_ia32_maskstored256">,
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Intrinsic<[], [llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty], []>;
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def int_x86_avx2_maskstore_q_256 :
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GCCBuiltin<"__builtin_ia32_maskstoreq256">,
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Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty], []>;
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}
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// Misc.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx2_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb256">,
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@ -7563,3 +7563,41 @@ let neverHasSideEffects = 1, mayStore = 1 in
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def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
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(ins i128mem:$dst, VR256:$src1, i8imm:$src2),
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"vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
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//===----------------------------------------------------------------------===//
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// VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
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//
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multiclass avx2_pmovmask<string OpcodeStr,
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Intrinsic IntLd128, Intrinsic IntLd256,
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Intrinsic IntSt128, Intrinsic IntSt256,
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PatFrag pf128, PatFrag pf256> {
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def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
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def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
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def mr : AVX28I<0x8e, MRMDestMem, (outs),
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(ins i128mem:$dst, VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
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def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
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(ins i256mem:$dst, VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
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}
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defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
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int_x86_avx2_maskload_d,
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int_x86_avx2_maskload_d_256,
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int_x86_avx2_maskstore_d,
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int_x86_avx2_maskstore_d_256,
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memopv4i32, memopv8i32>;
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defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
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int_x86_avx2_maskload_q,
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int_x86_avx2_maskload_q_256,
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int_x86_avx2_maskstore_q,
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int_x86_avx2_maskstore_q_256,
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memopv2i64, memopv4i64>, VEX_W;
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@ -902,3 +902,67 @@ define <4 x i64> @test_x86_avx2_vinserti128(<4 x i64> %a0, <2 x i64> %a1) {
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64>, <2 x i64>, i8) nounwind readnone
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define <2 x i64> @test_x86_avx2_maskload_q(i8* %a0, <2 x i64> %a1) {
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; CHECK: vpmaskmovq
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%res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.avx2.maskload.q(i8*, <2 x i64>) nounwind readonly
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define <4 x i64> @test_x86_avx2_maskload_q_256(i8* %a0, <4 x i64> %a1) {
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; CHECK: vpmaskmovq
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%res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.avx2.maskload.q.256(i8*, <4 x i64>) nounwind readonly
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define <4 x i32> @test_x86_avx2_maskload_d(i8* %a0, <4 x i32> %a1) {
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; CHECK: vpmaskmovd
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%res = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.avx2.maskload.d(i8*, <4 x i32>) nounwind readonly
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define <8 x i32> @test_x86_avx2_maskload_d_256(i8* %a0, <8 x i32> %a1) {
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; CHECK: vpmaskmovd
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%res = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
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ret <8 x i32> %res
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}
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declare <8 x i32> @llvm.x86.avx2.maskload.d.256(i8*, <8 x i32>) nounwind readonly
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define void @test_x86_avx2_maskstore_q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2) {
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; CHECK: vpmaskmovq
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call void @llvm.x86.avx2.maskstore.q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2)
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ret void
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}
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declare void @llvm.x86.avx2.maskstore.q(i8*, <2 x i64>, <2 x i64>) nounwind
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define void @test_x86_avx2_maskstore_q_256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2) {
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; CHECK: vpmaskmovq
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call void @llvm.x86.avx2.maskstore.q.256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2)
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ret void
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}
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declare void @llvm.x86.avx2.maskstore.q.256(i8*, <4 x i64>, <4 x i64>) nounwind
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define void @test_x86_avx2_maskstore_d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2) {
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; CHECK: vpmaskmovd
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call void @llvm.x86.avx2.maskstore.d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2)
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ret void
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}
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declare void @llvm.x86.avx2.maskstore.d(i8*, <4 x i32>, <4 x i32>) nounwind
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define void @test_x86_avx2_maskstore_d_256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2) {
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; CHECK: vpmaskmovd
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call void @llvm.x86.avx2.maskstore.d.256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2)
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ret void
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}
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declare void @llvm.x86.avx2.maskstore.d.256(i8*, <8 x i32>, <8 x i32>) nounwind
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