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Allow explicit physical registers for implicit operands.
llvm-svn: 6468
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parent
2d906f4550
commit
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@ -23,6 +23,7 @@ extern const TargetInstrDescriptor *TargetInstrDescriptors;
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// Constructor for instructions with variable #operands
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MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
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: opCode(OpCode),
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opCodeFlags(0),
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operands(numOperands, MachineOperand()),
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numImplicitRefs(0)
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{
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@ -36,6 +37,7 @@ MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
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MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
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bool XX, bool YY)
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: opCode(Opcode),
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opCodeFlags(0),
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numImplicitRefs(0)
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{
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operands.reserve(numOperands);
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@ -47,6 +49,7 @@ MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
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unsigned numOperands)
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: opCode(Opcode),
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opCodeFlags(0),
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numImplicitRefs(0)
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{
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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@ -60,7 +63,7 @@ bool MachineInstr::OperandsComplete() const
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{
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int NumOperands = TargetInstrDescriptors[opCode].numOperands;
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if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
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return true; // Broken!
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return true; // Broken: we have all the operands of this instruction!
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return false;
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}
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@ -141,6 +144,13 @@ MachineInstr::SetRegForOperand(unsigned i, int regNum)
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insertUsedReg(regNum);
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}
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void
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MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
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{
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getImplicitOp(i).setRegForValue(regNum);
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insertUsedReg(regNum);
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}
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// Subsitute all occurrences of Value* oldVal with newVal in all operands
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// and all implicit refs. If defsOnly == true, substitute defs only.
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