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[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
Add a caller which exhausts regs then calls another function. This allows getCalleePreservedRegs to be tested. llvm-svn: 356122
This commit is contained in:
Alex Bradbury
parent
013902e369
commit
b2f7abd4ce
@ -1,4 +1,3 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=ILP32-LP64
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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@ -8,8 +7,11 @@
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; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
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define void @foo() {
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; ILP32-LP64-LABEL: foo:
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; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
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; something appropriate.
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define void @callee() {
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; ILP32-LP64-LABEL: callee:
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; ILP32-LP64: # %bb.0:
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; ILP32-LP64-NEXT: lui a0, %hi(var)
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; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
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@ -82,3 +84,24 @@ define void @foo() {
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store volatile [32 x float] %val, [32 x float]* @var
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ret void
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}
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; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
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; something appropriate.
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;
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; For the soft float ABIs, no floating point registers are preserved, and
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; codegen will use only ft0 in the body of caller.
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define void @caller() {
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; ILP32-LP64-LABEL: caller:
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; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
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; ILP32-LP64-NOT: fs{{[0-9]+}}
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; ILP32-LP64-NOT: fa{{[0-9]+}}
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; ILP32-LP64: ret
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; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
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; ILP32-LP64-NOT: fs{{[0-9]+}}
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; ILP32-LP64-NOT: fa{{[0-9]+}}
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%val = load [32 x float], [32 x float]* @var
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call void @callee()
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store volatile [32 x float] %val, [32 x float]* @var
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ret void
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}
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@ -8,8 +8,11 @@
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; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
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define void @foo() {
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; ILP32-LP64-LABEL: foo:
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; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
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; something appropriate.
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define void @callee() {
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; ILP32-LP64-LABEL: callee:
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; ILP32-LP64: # %bb.0:
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; ILP32-LP64-NEXT: lui a0, %hi(var)
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; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
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@ -82,3 +85,24 @@ define void @foo() {
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store volatile [32 x double] %val, [32 x double]* @var
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ret void
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}
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; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
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; something appropriate.
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;
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; For the soft float ABIs, no floating point registers are preserved, and
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; codegen will use only ft0 in the body of caller.
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define void @caller() {
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; ILP32-LP64-LABEL: caller:
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; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
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; ILP32-LP64-NOT: fs{{[0-9]+}}
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; ILP32-LP64-NOT: fa{{[0-9]+}}
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; ILP32-LP64: ret
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; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
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; ILP32-LP64-NOT: fs{{[0-9]+}}
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; ILP32-LP64-NOT: fa{{[0-9]+}}
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%val = load [32 x double], [32 x double]* @var
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call void @callee()
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store volatile [32 x double] %val, [32 x double]* @var
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ret void
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}
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@ -9,8 +9,11 @@
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@var = global [32 x i32] zeroinitializer
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define void @foo() {
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; RV32I-LABEL: foo:
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; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
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; something appropriate.
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define void @callee() {
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; RV32I-LABEL: callee:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -80
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; RV32I-NEXT: sw s0, 76(sp)
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@ -28,7 +31,7 @@ define void @foo() {
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; RV32I-NEXT: lui a0, %hi(var)
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; RV32I-NEXT: addi a1, a0, %lo(var)
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;
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; RV32I-WITH-FP-LABEL: foo:
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; RV32I-WITH-FP-LABEL: callee:
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; RV32I-WITH-FP: # %bb.0:
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; RV32I-WITH-FP-NEXT: addi sp, sp, -80
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; RV32I-WITH-FP-NEXT: sw ra, 76(sp)
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@ -48,7 +51,7 @@ define void @foo() {
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; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
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; RV32I-WITH-FP-NEXT: addi a1, a0, %lo(var)
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;
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; RV64I-LABEL: foo:
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; RV64I-LABEL: callee:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -144
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; RV64I-NEXT: sd s0, 136(sp)
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@ -66,7 +69,7 @@ define void @foo() {
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; RV64I-NEXT: lui a0, %hi(var)
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; RV64I-NEXT: addi a1, a0, %lo(var)
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;
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; RV64I-WITH-FP-LABEL: foo:
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; RV64I-WITH-FP-LABEL: callee:
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; RV64I-WITH-FP: # %bb.0:
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; RV64I-WITH-FP-NEXT: addi sp, sp, -160
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; RV64I-WITH-FP-NEXT: sd ra, 152(sp)
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@ -89,3 +92,126 @@ define void @foo() {
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store volatile [32 x i32] %val, [32 x i32]* @var
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ret void
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}
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; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
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; something appropriate.
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define void @caller() {
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; RV32I-LABEL: caller:
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; RV32I: lui a0, %hi(var)
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; RV32I-NEXT: addi s1, a0, %lo(var)
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; RV32I: sw a0, 8(sp)
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; RV32I-NEXT: lw s2, 84(s1)
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; RV32I-NEXT: lw s3, 88(s1)
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; RV32I-NEXT: lw s4, 92(s1)
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; RV32I-NEXT: lw s5, 96(s1)
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; RV32I-NEXT: lw s6, 100(s1)
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; RV32I-NEXT: lw s7, 104(s1)
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; RV32I-NEXT: lw s8, 108(s1)
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; RV32I-NEXT: lw s9, 112(s1)
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; RV32I-NEXT: lw s10, 116(s1)
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; RV32I-NEXT: lw s11, 120(s1)
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; RV32I-NEXT: lw s0, 124(s1)
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; RV32I-NEXT: call callee
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; RV32I-NEXT: sw s0, 124(s1)
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; RV32I-NEXT: sw s11, 120(s1)
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; RV32I-NEXT: sw s10, 116(s1)
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; RV32I-NEXT: sw s9, 112(s1)
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; RV32I-NEXT: sw s8, 108(s1)
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; RV32I-NEXT: sw s7, 104(s1)
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; RV32I-NEXT: sw s6, 100(s1)
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; RV32I-NEXT: sw s5, 96(s1)
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; RV32I-NEXT: sw s4, 92(s1)
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; RV32I-NEXT: sw s3, 88(s1)
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; RV32I-NEXT: sw s2, 84(s1)
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; RV32I-NEXT: lw a0, 8(sp)
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;
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; RV32I-WITH-FP-LABEL: caller:
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; RV32I-WITH-FP: addi s0, sp, 144
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; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
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; RV32I-WITH-FP-NEXT: addi s1, a0, %lo(var)
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; RV32I-WITH-FP: sw a0, -140(s0)
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; RV32I-WITH-FP-NEXT: lw s5, 88(s1)
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; RV32I-WITH-FP-NEXT: lw s6, 92(s1)
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; RV32I-WITH-FP-NEXT: lw s7, 96(s1)
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; RV32I-WITH-FP-NEXT: lw s8, 100(s1)
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; RV32I-WITH-FP-NEXT: lw s9, 104(s1)
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; RV32I-WITH-FP-NEXT: lw s10, 108(s1)
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; RV32I-WITH-FP-NEXT: lw s11, 112(s1)
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; RV32I-WITH-FP-NEXT: lw s2, 116(s1)
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; RV32I-WITH-FP-NEXT: lw s3, 120(s1)
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; RV32I-WITH-FP-NEXT: lw s4, 124(s1)
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; RV32I-WITH-FP-NEXT: call callee
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; RV32I-WITH-FP-NEXT: sw s4, 124(s1)
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; RV32I-WITH-FP-NEXT: sw s3, 120(s1)
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; RV32I-WITH-FP-NEXT: sw s2, 116(s1)
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; RV32I-WITH-FP-NEXT: sw s11, 112(s1)
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; RV32I-WITH-FP-NEXT: sw s10, 108(s1)
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; RV32I-WITH-FP-NEXT: sw s9, 104(s1)
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; RV32I-WITH-FP-NEXT: sw s8, 100(s1)
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; RV32I-WITH-FP-NEXT: sw s7, 96(s1)
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; RV32I-WITH-FP-NEXT: sw s6, 92(s1)
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; RV32I-WITH-FP-NEXT: sw s5, 88(s1)
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; RV32I-WITH-FP-NEXT: lw a0, -140(s0)
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;
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; RV64I-LABEL: caller:
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; RV64I: lui a0, %hi(var)
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; RV64I-NEXT: addi s1, a0, %lo(var)
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; RV64I: sd a0, 0(sp)
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; RV64I-NEXT: lw s2, 84(s1)
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; RV64I-NEXT: lw s3, 88(s1)
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; RV64I-NEXT: lw s4, 92(s1)
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; RV64I-NEXT: lw s5, 96(s1)
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; RV64I-NEXT: lw s6, 100(s1)
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; RV64I-NEXT: lw s7, 104(s1)
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; RV64I-NEXT: lw s8, 108(s1)
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; RV64I-NEXT: lw s9, 112(s1)
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; RV64I-NEXT: lw s10, 116(s1)
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; RV64I-NEXT: lw s11, 120(s1)
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; RV64I-NEXT: lw s0, 124(s1)
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; RV64I-NEXT: call callee
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; RV64I-NEXT: sw s0, 124(s1)
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; RV64I-NEXT: sw s11, 120(s1)
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; RV64I-NEXT: sw s10, 116(s1)
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; RV64I-NEXT: sw s9, 112(s1)
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; RV64I-NEXT: sw s8, 108(s1)
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; RV64I-NEXT: sw s7, 104(s1)
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; RV64I-NEXT: sw s6, 100(s1)
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; RV64I-NEXT: sw s5, 96(s1)
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; RV64I-NEXT: sw s4, 92(s1)
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; RV64I-NEXT: sw s3, 88(s1)
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; RV64I-NEXT: sw s2, 84(s1)
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; RV64I-NEXT: ld a0, 0(sp)
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;
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; RV64I-WITH-FP-LABEL: caller:
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; RV64I-WITH-FP: addi s0, sp, 288
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; RV64I-WITH-FP-NEXT: lui a0, %hi(var)
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; RV64I-WITH-FP-NEXT: addi s1, a0, %lo(var)
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; RV64I-WITH-FP: sd a0, -280(s0)
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; RV64I-WITH-FP-NEXT: lw s5, 88(s1)
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; RV64I-WITH-FP-NEXT: lw s6, 92(s1)
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; RV64I-WITH-FP-NEXT: lw s7, 96(s1)
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; RV64I-WITH-FP-NEXT: lw s8, 100(s1)
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; RV64I-WITH-FP-NEXT: lw s9, 104(s1)
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; RV64I-WITH-FP-NEXT: lw s10, 108(s1)
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; RV64I-WITH-FP-NEXT: lw s11, 112(s1)
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; RV64I-WITH-FP-NEXT: lw s2, 116(s1)
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; RV64I-WITH-FP-NEXT: lw s3, 120(s1)
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; RV64I-WITH-FP-NEXT: lw s4, 124(s1)
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; RV64I-WITH-FP-NEXT: call callee
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; RV64I-WITH-FP-NEXT: sw s4, 124(s1)
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; RV64I-WITH-FP-NEXT: sw s3, 120(s1)
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; RV64I-WITH-FP-NEXT: sw s2, 116(s1)
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; RV64I-WITH-FP-NEXT: sw s11, 112(s1)
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; RV64I-WITH-FP-NEXT: sw s10, 108(s1)
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; RV64I-WITH-FP-NEXT: sw s9, 104(s1)
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; RV64I-WITH-FP-NEXT: sw s8, 100(s1)
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; RV64I-WITH-FP-NEXT: sw s7, 96(s1)
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; RV64I-WITH-FP-NEXT: sw s6, 92(s1)
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; RV64I-WITH-FP-NEXT: sw s5, 88(s1)
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; RV64I-WITH-FP-NEXT: ld a0, -280(s0)
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%val = load [32 x i32], [32 x i32]* @var
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call void @callee()
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store volatile [32 x i32] %val, [32 x i32]* @var
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ret void
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}
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